BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Belgium
1 × Greece
1 × United Kingdom
2 × Canada
2 × Israel
22 × USA
5 × France
5 × Germany
Collaborated with:
A.L.Sangiovanni-Vincentelli A.Mishchenko R.Hojati P.C.McGeer W.K.C.Lam A.Saldanha Y.Kukimoto R.Murgai A.Aziz J.R.Jiang V.Singhal F.Mo E.I.Goldberg T.Villa R.H.J.M.Otten S.Tasiran T.R.Shiple Y.Jiang R.P.Kurshan N.V.Shenoy Y.Watanabe C.W.Moon S.Ray M.R.Prasad R.K.Ranjan S.Chatterjee A.R.Newton H.Wang N.Eén J.V.Sanghavi H.Savoj S.C.Krishnan F.Balarin S.P.Khatri J.Baumgartner H.Mony M.L.Case N.Yevtushenko Y.Dai K.Khoo A.P.Hurst S.Matic A.Tabbara A.J.Isles G.S.Manku P.Sawkar R.B.Mueller-Thuns Y.Matsunaga T.Kam F.Somenzi S.Qadeer V.N.Kravets A.Kuehlmann J.S.Zhang M.Chrzanowska-Jeske D.Jongeneel K.Sanwal A.Puri P.Varaiya C.Pixley R.L.Rudell H.J.Touati M.Chiodo L.Lavagno K.J.Singh A.A.Malik A.R.Wang Y.Yang S.Sinha A.G.Veneris D.E.Smith A.Petrenko A.Mehrotra R.Alur T.A.Henzinger S.K.Rajamani M.D.DiBenedetto H.Harkness Y.Nishizaki P.K.Nalla P.Chauhan N.Sharma S.Jang C.Chen A.Narayan K.L.McMillan S.Cheng G.D.Hachtel S.A.Edwards A.Pardo S.Sarwary G.Swamy
Talks about:
use (14) time (11) logic (10) function (9) verif (9) state (9) base (9) sequenti (8) circuit (8) synthesi (7)

Person: Robert K. Brayton

DBLP DBLP: Brayton:Robert_K=

Contributed to:

DAC 20152015
DATE 20132013
DATE 20122012
CAV 20102010
DATE 20092009
DAC 20082008
DAC 20072007
DAC 20062006
DATE 20052005
CAV 20042004
DAC 20042004
DAC 20032003
DATE 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DAC 19991999
DATE 19991999
CAV 19981998
DAC 19981998
DATE 19981998
CAV 19971997
DAC 19971997
CAV 19961996
DAC 19961996
CAV 19951995
DAC 19951995
CAV 19941994
DAC 19941994
EDAC-ETC-EUROASIC 19941994
ICALP 19941994
CAV 19931993
DAC 19931993
CAV 19921992
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19891989

Wrote 83 papers:

DAC-2015-DaiKB #equivalence
Sequential equivalence checking of clock-gated circuits (YYD, KYK, RKB), p. 6.
DATE-2013-MishchenkoEBBMN #abstraction #named #revisited
GLA: gate-level abstraction revisited (AM, NE, RKB, JB, HM, PKN), pp. 1399–1404.
DATE-2013-MishchenkoEBCCS
A semi-canonical form for sequential AIGs (AM, NE, RKB, MLC, PC, NS), pp. 797–802.
DATE-2012-RayB #scalability #verification
Scalable progress verification in credit-based flow-control systems (SR, RKB), pp. 905–910.
DATE-2012-RayMEBJC
Mapping into LUT structures (SR, AM, NE, RKB, SJ, CC), pp. 1579–1584.
CAV-2010-BraytonM #named #verification
ABC: An Academic Industrial-Strength Verification Tool (RKB, AM), pp. 24–40.
DATE-2009-MonyBMB #identification #scalability
Speculative reduction-based scalable redundancy identification (HM, JB, AM, RKB), pp. 1674–1679.
DATE-2009-YangSVBS #approximate #logic
Sequential logic rectifications with approximate SPFDs (YSY, SS, AGV, RKB, DES), pp. 1698–1703.
DAC-2008-CaseKMB
Merging nodes under sequential observability (MLC, VNK, AM, RKB), pp. 540–545.
DAC-2008-HurstMB #constraints #scalability
Scalable min-register retiming under timing and initializability constraints (APH, AM, RKB), pp. 534–539.
DAC-2007-ChatterjeeMBK #equivalence #on the #proving
On Resolution Proofs for Combinational Equivalence (SC, AM, RKB, AK), pp. 600–605.
DAC-2006-MishchenkoCB #fresh look #logic #synthesis
DAG-aware AIG rewriting a fresh look at combinational logic synthesis (AM, SC, RKB), pp. 532–535.
DAC-2006-ZhangMBC #detection #representation #satisfiability #scalability #simulation #symmetry #using
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability (JSZ, AM, RKB, MCJ), pp. 510–515.
DATE-2005-MishchenkoB #network #optimisation #satisfiability
SAT-Based Complete Don’t-Care Computation for Network Optimization (AM, RKB), pp. 412–417.
DATE-2005-MishchenkoBJVY #equation #performance #using
Efficient Solution of Language Equations Using Partitioned Representations (AM, RKB, JHRJ, TV, NY), pp. 418–423.
CAV-2004-JiangB #dependence #functional #reduction #verification
Functional Dependency for Verification Reduction (JHRJ, RKB), pp. 268–280.
DAC-2004-MoB #design
A timing-driven module-based chip design flow (FM, RKB), pp. 67–70.
DAC-2003-JiangMB #evaluation #logic
Generalized cofactoring for logic function evaluation (YJ, SM, RKB), pp. 155–158.
DATE-2003-JiangMB #algebra #multi
Reducing Multi-Valued Algebraic Operations to Binary (JHRJ, AM, RKB), pp. 10752–10757.
DATE-2003-YevtushenkoVBPS #equation
Equisolvability of Series vs. Controller’s Topology in Synchronous Language Equations (NY, TV, RKB, AP, ALSV), pp. 11154–11155.
DAC-2002-JiangB #logic #simulation #specification #synthesis #using
Software synthesis from synchronous specifications using logic simulation techniques (YJ, RKB), pp. 319–324.
DAC-2002-MoB
River PLAs: a regular circuit structure (FM, RKB), pp. 201–206.
DATE-2002-GoldbergPB #algorithm #problem #satisfiability #symmetry #using
Using Problem Symmetry in Search Based Satisfiability Algorithms (EIG, MRP, RKB), pp. 134–141.
DATE-2001-GoldbergPB #equivalence #satisfiability #using
Using SAT for combinational equivalence checking (EIG, MRP, RKB), pp. 114–121.
DAC-2000-JongeneelWBO
Area and search space control for technology mapping (DJJ, YW, RKB, RHJMO), pp. 86–91.
DAC-1999-KhatriMBOS #layout #novel
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.
DAC-1999-TabbaraBN #constraints #trade-off
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (AT, RKB, ARN), pp. 725–730.
DATE-1999-RanjanSSB #using #verification
Using Combinational Verification for Sequential Circuits (RKR, VS, FS, RKB), pp. 138–144.
CAV-1998-IslesHB #infinity #memory management
Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory (AJI, RH, RKB), pp. 256–267.
CAV-1998-MankuHB #model checking #symmetry
Structural Symmetry and Model Checking (GSM, RH, RKB), pp. 159–171.
DAC-1998-KukimotoB #analysis #functional
Hierarchical Functional Timing Analysis (YK, RKB), pp. 580–585.
DAC-1998-KukimotoBS #graph
Delay-Optimal Technology Mapping by DAG Covering (YK, RKB, PS), pp. 348–351.
DAC-1998-OttenB #performance
Planning for Performance (RHJMO, RKB), pp. 122–127.
DATE-1998-GoldbergKB #functional #specification #verification
Combinational Verification based on High-Level Functional Specifications (EIG, YK, RKB), pp. 803–808.
CAV-1997-AlurBHQR #partial order #reduction
Partial-Order Reduction in Symbolic State Space Exploration (RA, RKB, TAH, SQ, SKR), pp. 340–351.
CAV-1997-TasiranB #case study #composition #named #verification
STARI: A Case Study in Compositional and Hierarchical Timing Verification (ST, RKB), pp. 191–201.
DAC-1997-KukimotoB #analysis #detection
Exact Required Time Analysis via False Path Detection (YK, RKB), pp. 220–225.
CAV-1996-AzizSSB #markov #verification
Verifying Continuous Time Markov Chains (AA, KS, VS, RKB), pp. 269–276.
CAV-1996-BraytonHSSACEKKPQRSSSV #named #synthesis #verification
VIS: A System for Verification and Synthesis (RKB, GDH, ALSV, FS, AA, STC, SAE, SPK, YK, AP, SQ, RKR, SS, TRS, GS, TV), pp. 428–432.
DAC-1996-KhatriNKMBS #automaton #nondeterminism
Engineering Change in a Non-Deterministic FSM Setting (SPK, AN, SCK, KLM, RKB, ALSV), pp. 451–456.
DAC-1996-SanghaviRBS #memory management #performance
High Performance BDD Package By Exploiting Memory Hiercharchy (JVS, RKR, RKB, ALSV), pp. 635–640.
CAV-1995-AzizBBDS #finite #state machine
Supervisory Control of Finite State Machines (AA, FB, RKB, MDD, AS), pp. 279–292.
CAV-1995-HojatiB #abstraction #automation #hardware
Automatic Datapath Abstraction In Hardware Systems (RH, RKB), pp. 98–113.
CAV-1995-KrishnanPBV #automaton #game studies
The Rabin Index and Chain Automata, with Applications to Automatas and Games (SCK, AP, RKB, PV), pp. 253–266.
DAC-1995-SinghalPRB
The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.
CAV-1994-HojatiMB #graph #using
Improving Language Containment Using Fairness Graphs (RH, RBMT, RKB), pp. 391–403.
CAV-1994-LamB #automaton
Criteria for the Simple Path Property in Timed Automata (WKCL, RKB), pp. 27–40.
DAC-1994-AzizBCHKKRSSTWBS #named #verification
HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.
DAC-1994-AzizTB #finite #state machine
BDD Variable Ordering for Interacting Finite State Machines (AA, ST, RKB), pp. 283–288.
DAC-1994-KamVBS #algorithm
A Fully Implicit Algorithm for Exact State Minimization (TK, TV, RKB, ALSV), pp. 684–690.
DAC-1994-LamBS #finite #state machine
Exact Minimum Cycle Times for Finite State Machines (WKCL, RKB, ALSV), pp. 100–105.
DAC-1994-MurgaiBS #composition #encoding #functional #using
Optimum Functional Decomposition Using Encoding (RM, RKB, ALSV), pp. 408–414.
DAC-1994-SaldanhaHMBS #optimisation #performance #using
Performance Optimization Using Exact Sensitization (AS, HH, PCM, RKB, ALSV), pp. 425–429.
DAC-1994-ShipleHSB #heuristic #using
Heuristic Minimization of BDDs Using Don’t Cares (TRS, RH, ALSV, RKB), pp. 225–231.
DAC-1994-WangB #automaton #network
Permissible Observability Relations in FSM Networks (HYW, RKB), pp. 677–683.
EDAC-1994-WatanabeB #automaton #nondeterminism #pseudo
State Minimization of Pseudo Non-Deterministic FSM’s (YW, RKB), pp. 184–191.
ICALP-1994-AzizSBBS
Equivalences for Fair Kripke Structures (AA, VS, FB, RKB, ALSV), pp. 364–375.
CAV-1993-Brayton #design #logic #synthesis #verification
Logic Synthesis and Design Verification (RKB), pp. 1–2.
CAV-1993-HojatiBK #debugging #design #using
BDD-Based Debugging Of Design Using Language Containment and Fair CTL (RH, RKB, RPK), pp. 41–58.
CAV-1993-LamB #automaton
Alternating RQ Timed Automata (WKCL, RKB), pp. 237–252.
DAC-1993-HojatiSBK #approach #model checking
A Unified Approach to Language Containment and Fair CTL Model Checking (RH, TRS, RKB, RPK), pp. 475–481.
DAC-1993-LamBS #modelling #using
Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions (WKCL, RKB, ALSV), pp. 128–134.
DAC-1993-LamSBS #fault #performance #trade-off
Delay Fault Coverage and Performance Tradeoffs (WKCL, AS, RKB, ALSV), pp. 446–452.
DAC-1993-MatsunagaMB #on the #transitive
On Computing the Transitive Closure of a State Transition Relation (YM, PCM, RKB), pp. 260–265.
DAC-1993-McGeerSBS #logic #named
Espresso-Signature: A New Exact Minimizer for Logic Functions (PCM, JVS, RKB, ALSV), pp. 618–624.
DAC-1993-MoonB
Elimination of Dynamic hazards by Factoring (CWM, RKB), pp. 7–13.
DAC-1993-MurgaiBS #array #programmable #synthesis
Sequential Synthesis for Table Look Up Programmable Gate Arrays (RM, RKB, ALSV), pp. 224–229.
DAC-1993-ShenoyBS #multi #pipes and filters
Resynthesis of Multi-Phase Pipelines (NVS, RKB, ALSV), pp. 490–496.
CAV-1992-HojatiTKB #performance #regular expression
Efficient ω-Regular Language Containment (RH, HJT, RPK, RKB), pp. 396–409.
CAV-1992-ShipleCSB #automation #composition #model checking #reduction
Automatic Reduction in CTL Compositional Model Checking (TRS, MC, ALSV, RKB), pp. 234–247.
DAC-1992-LavagnoMBS #graph #problem
Solving the State Assignment Problem for Signal Transition Graphs (LL, CWM, RKB, ALSV), pp. 568–572.
DAC-1992-MurgaiBS #algorithm #multi #synthesis
An Improved Synthesis Algorithm for Multiplexor-Based PGA’s (RM, RKB, ALSV), pp. 380–386.
DAC-1992-SaldanhaBS #equivalence #generative #robust #testing
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation (AS, RKB, ALSV), pp. 173–176.
DAC-1992-SaldanhaBS92a #algorithm #revisited
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited (AS, RKB, ALSV), pp. 245–248.
DAC-1992-ShenoySBS #equivalence #on the
On the Temporal Equivalence of Sequential Circuits (NVS, KJS, RKB, ALSV), pp. 405–409.
DAC-1991-SaldanhaVBS #constraints #encoding #framework
A Framework for Satisfying Input and Output Encoding Constraints (AS, TV, RKB, ALSV), pp. 170–175.
DAC-1990-MalikBNS #logic #multi
Reduced Offsets for Two-Level Multi-Valued Logic Minimization (AAM, RKB, ARN, ALSV), pp. 290–296.
DAC-1990-McGeerB #analysis #network
Timing Analysis in Precharge/Unate Networks (PCM, RKB), pp. 124–129.
DAC-1990-MurgaiNSBS #array #logic #programmable #synthesis
Logic Synthesis for Programmable Gate Arrays (RM, YN, NVS, RKB, ALSV), pp. 620–625.
DAC-1990-SavojB #multi #network #using
The Use of Observability and External Don’t Cares for the Simplification of Multi-Level Networks (HS, RKB), pp. 297–301.
DAC-1989-McGeerB #logic #performance
Efficient Prime Factorization of Logic Expressions (PCM, RKB), pp. 221–225.
DAC-1989-McGeerB89a #algorithm #network #performance
Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network (PCM, RKB), pp. 561–567.
DAC-1989-SaldanhaWBS #logic #multi #using
Multi-level Logic Simplification Using Don’t Cares and Filters (AS, ARW, RKB, ALSV), pp. 277–282.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.