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Travelled to:
2 × USA
4 × Germany
5 × France
Collaborated with:
F.Catthoor S.Mamagkakis A.Bartzas D.Atienza I.Anagnostopoulos C.E.Goutis J.M.Mendias K.Siozios V.F.Pavlidis A.Thanailakis V.Tsoutsouras G.Lyras D.Rodopoulos A.Papanikolaou G.Kathareios G.Economakos S.Xydis I.Koutras N.D.Liveris N.D.Zervas M.D.Galanis A.Milidonis G.Theodoridis C.Poucet M.Dasygenis E.Brockmeyer B.Durinck Y.Iosifidis A.Mallik E.d.Greef G.Pouiklis
Talks about:
methodolog (6) memori (6) applic (5) dynam (5) platform (4) perform (3) explor (3) design (3) optim (3) base (3)

Person: Dimitrios Soudris

DBLP DBLP: Soudris:Dimitrios

Contributed to:

DAC 20132013
DATE 20132013
DATE 20122012
DAC 20102010
DATE 20102010
DATE 20092009
DATE 20072007
DATE 20062006
DATE 20052005
DATE 20052004
DATE v1 20042004
DATE 20022002

Wrote 13 papers:

DAC-2013-AnagnostopoulosTBS #distributed #manycore #platform #resource management #runtime
Distributed run-time resource management for malleable applications on many-core platforms (IA, VT, AB, DS), p. 6.
DATE-2013-LyrasRPS #multi #scalability #simulation
Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems (GL, DR, AP, DS), pp. 655–658.
DATE-2012-AnagnostopoulosBKS #distributed #divide and conquer #manycore #platform #runtime
A divide and conquer based distributed run-time mapping methodology for many-core platforms (IA, AB, GK, DS), pp. 111–116.
DAC-2010-IosifidisMMGBSC #automation #framework #memory management #optimisation #parallel #platform
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms (YI, AM, SM, EdG, AB, DS, FC), pp. 549–554.
DATE-2010-EconomakosXKS #component #configuration management #synthesis
Construction of dual mode components for reconfiguration aware high-level synthesis (GE, SX, IK, DS), pp. 1357–1360.
DATE-2009-SioziosPS #3d #architecture
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs (KS, VFP, DS), pp. 172–177.
DATE-2007-MamagkakisSC #design #middleware #optimisation #protocol
Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns (SM, DS, FC), pp. 1036–1041.
DATE-2006-BartzasMPACST #data type #design #energy #network #refinement
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications (AB, SM, GP, DA, FC, DS, AT), pp. 740–745.
DATE-2006-MamagkakisAPCSM #automation #embedded #memory management
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems (SM, DA, CP, FC, DS, JMM), pp. 874–875.
DATE-2005-DasygenisBDCST #energy #memory management #performance
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck (MD, EB, BD, FC, DS, AT), pp. 946–947.
DATE-2005-GalanisMTSG04 #clustering #configuration management #hybrid
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms (MDG, AM, GT, DS, CEG), pp. 247–252.
DATE-v1-2004-AtienzaMCMS #design #memory management #multi #network
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications (DA, SM, FC, JMM, DS), pp. 532–537.
DATE-2002-LiverisZSG #performance #program transformation
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications (NDL, NDZ, DS, CEG), pp. 977–983.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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