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Travelled to:
1 × USA
Collaborated with:
J.Dussault M.M.Tong
Talks about:
synthesi (1) design (1) level (1) tool (1) high (1) chip (1) mos (1)

Person: Chi-Chang Liaw

DBLP DBLP: Liaw:Chi=Chang

Contributed to:

DAC 19841984

Wrote 1 papers:

DAC-1984-DussaultLT #design #synthesis
A high level synthesis tool for MOS chip design (JPD, CCL, MMT), pp. 308–314.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.