Stem mos$ (all stems)

68 papers:

SPLC-2015-MazoMRST #named #product line

VariaMos: an extensible tool for engineering (dynamic) product lines (RM, JCMF, LR, CS, GT), pp. 374–379.

DAC-2011-CevreroRSBIL #library #logic #power management #standard

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library (AC, FR, MS, SB, PI, YL), pp. 1014–1019.

DATE-2007-AggarwalO #modelling #parametricity #reuse

Simulation-based reusable posynomial models for MOS transistor parameters (VA, UMO), pp. 69–74.

DATE-1999-RibasC #clustering #modelling

Digital MOS Circuit Partitioning with Symbolic Modeling (LR, JC), pp. 503–508.

DAC-1996-RoychowdhuryM #scalability

Homotopy Techniques for Obtaining a DC Solution of Large-Scale MOS Circuits (JSR, RCM), pp. 286–291.

EDAC-1994-FrosslK #simulation

A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation (JF, TK), pp. 343–348.

DAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case

An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.

DAC-1991-LimquecoM #logic #network #optimisation

Logic Optimization of MOS Networks (JCL, SM), pp. 464–469.

DAC-1991-ShihK #approach #equation #named #performance #using

ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach (YHS, SMK), pp. 20–25.

DAC-1990-Domic #layout #synthesis

Layout Synthesis of MOS Digital Cells (AD), pp. 241–245.

DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic

Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.

DAC-1989-ChoB #fault #generative #simulation

Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation (KC, REB), pp. 418–423.

DAC-1989-SalzH #incremental #named

IRSIM: An Incremental MOS Switch-Level Simulator (AS, MH), pp. 173–178.

DAC-1988-Adler #logic #simulation

A Dynamically-Directed Switch Model for MOS Logic Simulation (DA), pp. 506–511.

DAC-1988-BaltusA #generative #named #performance

SOLO: A Generator of Efficient Layouts from Optimized MOS Circuit Schematics (DGB, JA), pp. 445–452.

DAC-1988-ChangCS #performance

An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits (FCC, CFC, PS), pp. 282–287.

LICS-1988-HoareG #correctness #logic

Partial Correctness of C-MOS Switching Circuits: An Exercise in Applied Logic (CARH, MJCG), pp. 28–36.

DAC-1987-BryantBBCS #named

COSMOS: A Compiled Simulator for MOS Circuits (REB, DLB, KSB, KC, TJS), pp. 9–16.

DAC-1987-Smith #hardware #scalability

A Hardware Switch Level Simulator for Large MOS Circuits (MTS), pp. 95–100.

DAC-1987-Weise #functional #verification

Functional Verification of MOS Circuits (DW), pp. 265–270.

DAC-1986-Beckett #c #modelling #network

MOS circuit models in Network C (WSB), pp. 171–178.

DAC-1986-VidigalND #analysis #integration #named #network

CINNAMON: coupled integration and nodal analysis of MOS networks (LMV, SRN, SWD), pp. 179–185.

DAC-1986-WunderlichR #fault #modelling #on the

On fault modeling for dynamic MOS circuits (HJW, WR), pp. 540–546.

DAC-1985-Lewis #hardware #simulation

A hardware engine for analogue mode simulation of MOS digital circuits (DML), pp. 345–351.

DAC-1985-Matson #megamodelling

Macromodeling of digital MOS VLSI Circuits (MDM), pp. 141–151.

DAC-1985-NgJ #approach #generative #graph

Generation of layouts from MOS circuit schematics: a graph theoretic approach (TKN, SLJ), pp. 39–45.

DAC-1985-ReddyRA #generative #testing

Transistor level test generation for MOS circuits (MKR, SMR, PA), pp. 825–828.

DAC-1985-SaucierT #layout

Systematic and optimized layout of MOS cells (GS, GT), pp. 53–61.

DAC-1985-Schaefer

A transistor-level logic-with-timing simulator for MOS circuits (TJS), pp. 762–765.

DAC-1984-ChuS #generative #independence #multi

A technology independent MOS multiplier generator (KcC, RS), pp. 90–97.

DAC-1984-dAbreuCF #design #named

Oracle — a simulator for Bipolar and MOS IC design (MAd, KLC, CTF), pp. 343–349.

DAC-1984-DussaultLT #design #synthesis

A high level synthesis tool for MOS chip design (JPD, CCL, MMT), pp. 308–314.

DAC-1984-EtiembleADB #algorithm #evaluation

Micro-computer oriented algorithms for delay evaluation of MOS gates (DE, VA, NHD, JCB), pp. 358–364.

DAC-1984-KawaiH #fault #simulation

An experimental MOS fault simulation program CSASIM (MK, JPH), pp. 2–9.

DAC-1984-Ousterhout #modelling

Switch-level delay models for digital MOS VLSI (JKO), pp. 542–548.

DAC-1984-TakahashiKYEF #logic #network #simulation

An MOS digital network model on a modified thevenin equivalent for logic simulation (TT, SK, OY, KE, HF), pp. 549–555.

DAC-1983-ChangA #consistency

Consistency checking for MOS/VLSI circuits (NSC, RA), pp. 732–733.

DAC-1983-JainA #generative #testing #using

Test generation for MOS circuits using D-algorithm (SKJ, VDA), pp. 64–70.

DAC-1983-LoNB #data type

A data structure for MOS circuits (CYL, HNN, AKB), pp. 619–624.

DAC-1983-OkazakiMY #multi

A multiple media delay simulator for MOS LSI circuits (KO, TM, TY), pp. 279–285.

DAC-1983-Ramachandran

An improved switch-level simulator for MOS circuits (VR), pp. 293–299.

DAC-1983-StevensA #logic #multi

BIMOS, an MOS oriented multi-level logic simulator (PS, GA), pp. 100–106.

DAC-1982-Agrawal #analysis

Synchronous path analysis in MOS circuit simulator (VDA), pp. 629–635.

DAC-1982-BoseKLNPW #fault

A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.

DAC-1982-LelarasmeeS #named #scalability

Relax: A new circuit for large scale MOS integrated circuits (EL, ALSV), pp. 682–687.

DAC-1982-LightnerH #algorithm #functional #megamodelling #testing

Implication algorithms for MOS switch level functional macromodeling implication and testing (MRL, GDH), pp. 691–698.

DAC-1982-TakashimaMCY #source code #verification

Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.

DAC-1981-Bryant #named

MOSSIM: A switch-level simulator for MOS LSI (REB), pp. 786–790.

DAC-1981-HoltH #logic

A MOS/LSI oriented logic simulator (DH, DH), pp. 280–287.

DAC-1981-NgGK #parametricity #verification

A timing verification system based on extracted MOS/VLSI circuit parameters (PN, WG, RK), pp. 288–292.

DAC-1981-SakauyeLRETSABW #design #set #source code

A set of programs for MOS design (GS, AL, JR, RE, JT, ESYS, EA, FB, PSW), pp. 435–442.

DAC-1981-SatoNTSOY #layout #named

MILD — A cell-based layout system for MOS-LSI (KS, TN, MT, HS, MO, TY), pp. 828–836.

DAC-1981-Sherwood #logic #modelling #simulation

A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge (WS), pp. 775–785.

DAC-1980-NhamB #multi

A multiple delay simulator for MOS LSI circuits (HNN, AKB), pp. 610–617.

DAC-1980-ShirakawaOHTO #layout #logic #random

A layout system for the random logic portion of MOS LSI (IS, NO, TH, ST, HO), pp. 92–99.

DAC-1979-AkinoSKN #simulation #verification

Circuit simulation and timing verification based on MOS/LSI mask information (TA, MS, YK, TN), pp. 88–94.

DAC-1979-BekeS #automation #interactive #layout #named

CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI (HB, WS), pp. 102–108.

DAC-1979-El-Ziq #fault #generative #network #performance #simulation #testing

Testing of MOS combinational networks a procedure for efficient fault simulation and test generation (YMEZ), pp. 162–170.

DAC-1978-El-Ziq #automation #constraints #design #logic #network

Logic design automation of MOS combinational networks with fan-in, fan-out constraints (YMEZ), pp. 240–249.

DAC-1977-El-ZiqS #automation #design #logic #network

Logic design automation of diagnosable MOS combinational logic networks (YMEZ, SYHS), pp. 205–215.

DAC-1977-KollerL #design #standard

The siemens-avesta-system for computer-aided design of MOS-standard cell circuits (KWK, UL), pp. 153–157.

DAC-1975-KozakGC

Operational features of an MOS timing simulator (PK, HKG, BRC), pp. 95–101.

DAC-1975-YoshizawaKK #array #heuristic

A heuristic procedure for ordering MOS arrays (HY, HK, KK), pp. 384–393.

DAC-1974-KozawaHISS #automation #generative #layout

Advanced LILAC — an Automated Layout Generation system for MOS/LSIs (TK, HH, TI, JS, SS), pp. 26–46.

DAC-1972-Banes #design #fault

Error free MOS/LSI design system (AVB), pp. 29–33.

DAC-1972-Mattison #low cost #quality

A high quality, low cost router for MOS/LSI (RLM), pp. 94–103.

DAC-1971-LarsenM #clustering #equation #layout #logic

Partitioning and ordering of logic equations for optimum MOS LSI device layout (RPL, LM), pp. 131–142.

DAC-1969-Lewallen #design

Mos LSI computer aided design system (DRL), pp. 91–101.