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Travelled to:
1 × France
1 × USA
Collaborated with:
S.Fang S.Huang C.Tseng J.Chen C.Hsu J.Liao W.Hsieh J.Yeh
Talks about:
power (4) model (2) librari (1) analysi (1) leakag (1) integr (1) design (1) compil (1) multi (1) depot (1)

Person: Chia-Chien Weng

DBLP DBLP: Weng:Chia=Chien

Contributed to:

DAC 20112011
DATE 20112011

Wrote 2 papers:

DAC-2011-HsuLFWHHY #analysis #design #manycore #modelling #named
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs (CWH, JLL, SCF, CCW, SYH, WTH, JCY), pp. 47–52.
DATE-2011-TsengHWFC #black box #compilation #library #modelling #power management
Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.