Travelled to:1 × Germany
3 × France
5 × USA
Collaborated with:K.Cheng K.Chen C.Tzeng W.Cheng S.Fang C.Weng M.Lee T.Hwang J.Yeh M.Tsai K.H.Tsai J.J.Lu T.Lee C.Tseng J.Chen C.Wang C.Wu C.Huang Y.Lin K.Tsai S.K.Sunter Y.Chou D.Kwai C.Hsu J.Liao W.Hsieh C.Lo M.Lee C.Li C.Lee S.Chang L.Denq C.Chi H.Hsu M.Chu J.Liou P.Huang H.Ma J.Bor C.Tien C.Wang Y.Kuo T.Chang
Talks about:power (6) design (5) test (5) base (4) integr (2) simul (2) oscil (2) model (2) error (2) delay (2)
Person: Shi-Yu Huang
DBLP: Huang:Shi=Yu
Contributed to:
2015
20122011201120092006200319981996Wrote 11 papers:
- DATE-2015-HuangTTC #architecture
- Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.
- DAC-2012-HuangLTCSCK #3d #testing
- Small delay testing for TSVs in 3-D ICs (SYH, YHL, KHT, WTC, SKS, YFC, DMK), pp. 1031–1036.
- DAC-2011-HsuLFWHHY #analysis #design #manycore #modelling #named
- PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs (CWH, JLL, SCF, CCW, SYH, WTH, JCY), pp. 47–52.
- DAC-2011-LiLWCDCHCLHHMBWTWKHC #interface #low cost #testing
- A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing (CFL, CYL, CHW, SLC, LMD, CCC, HJH, MYC, JJL, SYH, PCH, HPM, JCB, CWW, CCT, CHW, YSK, CTH, TYC), pp. 771–776.
- DATE-2011-TsengHWFC #black box #compilation #library #modelling #power management
- Black-box leakage power modeling for cell library and SRAM compiler (CKT, SYH, CCW, SCF, JJC), pp. 637–642.
- DATE-2009-TzengH #named
- QC-Fill: An X-Fill method for quick-and-cool scan test (CWT, SYH), pp. 1142–1147.
- DAC-2006-WangLLYHWH #design #framework #network #platform #security
- A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
- DATE-2003-LeeHH #composition #design #finite #power management #state machine
- Decomposition of Extended Finite State Machine for Low Power Design (ML, TH, SYH), pp. 11152–11153.
- DAC-1998-HuangCCL #design #fault
- Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
- DAC-1996-HuangCC #fault #verification
- Error Correction Based on Verification Techniques (SYH, KCC, KTC), pp. 258–261.
- DAC-1996-HuangCCL #generative #simulation
- Compact Vector Generation for Accurate Power Simulation (SYH, KCC, KTC, TCL), pp. 161–164.