Travelled to:5 × USA
Collaborated with:Y.I.Ismail N.Menezes C.V.Kashyap F.Dartu K.Killpack P.Mukherjee P.Li M.H.Chowdhury S.Mei E.Chiprout U.Choudhury N.Hakim
Talks about:circuit (3) model (3) approxim (2) effect (2) time (2) rlck (2) cell (2) properti (1) statist (1) respons (1)
Person: Chirayu S. Amin
DBLP: Amin:Chirayu_S=
Contributed to:
20142008200620052003Wrote 7 papers:
- DAC-2014-MukherjeeAL #approximate
- Approximate property checking of mixed-signal circuits (PM, CSA, PL), p. 6.
- DAC-2008-MenezesKA #grid #power management #verification
- A “true” electrical cell model for timing, noise, and power grid verification (NM, CVK, CSA), pp. 462–467.
- DAC-2006-AminKMKC #library #multi
- A multi-port current source model for multiple-input switching effects in CMOS library cells (CSA, CVK, NM, KK, EC), pp. 247–252.
- DAC-2005-AminID #approximate #using
- Piece-wise approximations of RLCK circuit responses using moment matching (CSA, YII, FD), pp. 927–932.
- DAC-2005-AminMKDCHI #analysis #how #question #statistics
- Statistical static timing analysis: how simple can we get? (CSA, NM, KK, FD, UC, NH, YII), pp. 652–657.
- DAC-2003-AminCI
- Realizable RLCK circuit crunching (CSA, MHC, YII), pp. 226–231.
- DAC-2003-MeiAI #order #performance #reduction
- Efficient model order reduction including skin effect (SM, CSA, YII), pp. 232–237.