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Travelled to:
1 × France
1 × USA
Collaborated with:
A.Cathelin D.Belot Y.Leclercq F.Clément S.Y.Borkar R.W.Brodersen J.Chern E.Naviasky C.Sodini
Talks about:
just (2) tomorrow (1) substrat (1) parasit (1) extract (1) circuit (1) integr (1) differ (1) analog (1) dead (1)

Person: D. Saias

DBLP DBLP: Saias:D=

Contributed to:

DAC 20062006
DATE 20022002

Wrote 2 papers:

DAC-2006-BorkarBCNSS #question
Tomorrow’s analog: just dead or just different? (SYB, RWB, JHC, EN, DS, CS), pp. 709–710.
DATE-2002-CathelinSBLC
Substrate Parasitic Extraction for RF Integrated Circuits (AC, DS, DB, YL, FC), p. 1107.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.