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Travelled to:
1 × Germany
Collaborated with:
S.P.Mohanty R.Velagapudi
Talks about:
nanoscal (1) datapath (1) circuit (1) physic (1) leakag (1) anneal (1) simul (1) optim (1) gate (1) awar (1)

Person: Elias Kougianos

DBLP DBLP: Kougianos:Elias

Contributed to:

DATE 20062006

Wrote 1 papers:

DATE-2006-MohantyVK #optimisation
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits (SPM, RV, EK), pp. 1191–1196.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.