Travelled to:1 × France
2 × Germany
Collaborated with:F.V.Fernández O.Guerra Á.Rodríguez-Vázquez M.Velasco-Jimenez R.Castro-López J.D.Rodríguez-García
Talks about:hierarch (2) circuit (2) analog (2) implement (1) composit (1) approach (1) algorihm (1) simplif (1) perform (1) generat (1)
Person: Elisenda Roca
DBLP: Roca:Elisenda
Contributed to:
201420001999Wrote 3 papers:
- DATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance
- Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
- DATE-2000-GuerraRFR #analysis #approach #scalability
- A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
- DATE-1999-GuerraRRFR #fault #generative
- An Accurate Error Control Mechanism for Simplification Before Generation Algorihms (OG, JDRG, ER, FVF, ÁRV), p. 412–?.