Proceedings of the 18th Conference and Exhibition on Design, Automation and Test in Europe
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Proceedings of the 18th Conference and Exhibition on Design, Automation and Test in Europe
DATE, 2014.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-2014,
	address       = "Dresden, Germany",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 18th Conference and Exhibition on Design, Automation and Test in Europe}",
	year          = 2014,
}

Contents (369 items)

DATE-2014-0001GWKAWG #optimisation #performance #runtime
Exploiting expendable process-margins in DRAMs for run-time performance optimization (KC, SG, CW, MK, BA, NW, KG), pp. 1–6.
DATE-2014-0002LLCXY #big data #data analysis #energy #network #performance
Energy efficient neural networks for big data analytics (YW, BL, RL, YC, NX, HY), pp. 1–2.
DATE-2014-AbeleinCEGRGRTUW #architecture #integration
Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures (UA, AC, PE, MG, FR, LRG, TR, JT, DU, HJW), pp. 1–6.
DATE-2014-AdlerAABG #debugging #logic
Facilitating timing debug by logic path correspondence (OA, EA, IA, IB, IG), pp. 1–6.
DATE-2014-AfacanAFDB #automation #design #modelling #optimisation
Model based hierarchical optimization strategies for analog design automation (EA, SA, FVF, GD, IFB), pp. 1–4.
DATE-2014-AghaeePE #3d #performance
An efficient temperature-gradient based burn-in technique for 3D stacked ICs (NA, ZP, PE), pp. 1–4.
DATE-2014-AguileraLFMSK #algorithm #clustering #multi #process
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking (PA, JL, AFF, KM, MJS, NSK), pp. 1–6.
DATE-2014-AhariAKT #architecture #configuration management #power management #using
A power-efficient reconfigurable architecture using PCM configuration technology (AA, HA, BK, MBT), pp. 1–6.
DATE-2014-AhmadC #performance #predict #simulation
Fast STA prediction-based gate-level timing simulation (TBA, MJC), pp. 1–6.
DATE-2014-AksanliR #data transformation
Providing regulation services and managing data center peak power budgets (BA, TR), pp. 1–4.
DATE-2014-AksoyFM #complexity #constant #design #multi #optimisation
Optimization of design complexity in time-multiplexed constant multiplications (LA, PFF, JCM), pp. 1–4.
DATE-2014-AlaghiH #performance #probability #using
Fast and accurate computation using stochastic circuits (AA, JPH), pp. 1–4.
DATE-2014-AlamPTSN #android #energy #optimisation
Energy optimization in Android applications through wakelock placement (FA, PRP, NT, NS, SN), pp. 1–4.
DATE-2014-AlhammadP #execution #manycore #parallel #predict #thread
Time-predictable execution of multithreaded applications on multicore systems (AA, RP), pp. 1–6.
DATE-2014-AlordaCB #embedded #power management #reliability
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications (BA, CC, SAB), pp. 1–6.
DATE-2014-AltmeyerD #analysis #correctness #on the #precise #probability
On the correctness, optimality and precision of Static Probabilistic Timing Analysis (SA, RID), pp. 1–6.
DATE-2014-AmaruGM #diagrams #performance
An efficient manipulation package for Biconditional Binary Decision Diagrams (LGA, PEG, GDM), pp. 1–6.
DATE-2014-AminifarBEP #co-evolution #design
Bandwidth-efficient controller-server co-design with stability guarantees (AA, EB, PE, ZP), pp. 1–6.
DATE-2014-AndradesRC #design #detection
Signature indexing of design layouts for hotspot detection (CA, MAR, CCC), pp. 1–6.
DATE-2014-AshammagariMH #configuration management #design #functional #performance #power management
Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design (ARA, HM, HH), pp. 1–6.
DATE-2014-AyariABCKR #predict
New implementions of predictive alternate analog/RF test with augmented model redundancy (HA, FA, SB, MC, VK, MR), pp. 1–4.
DATE-2014-AzimCPF #communication #distributed #generative #multi #realtime
Generation of communication schedules for multi-mode distributed real-time applications (AA, GC, RP, SF), pp. 1–6.
DATE-2014-BahrebarS #approach #network
Improving hamiltonian-based routing methods for on-chip networks: A turn model approach (PB, DS), pp. 1–4.
DATE-2014-BaiS #network
Isochronous networks by construction (YB, KS), pp. 1–6.
DATE-2014-BalckGP #generative #modelling #protocol #testing #using
Model-based protocol log generation for testing a telecommunication test harness using CLP (KB, OG, JP), pp. 1–4.
DATE-2014-BanagaayaAST #network #order #reduction
Implicit index-aware model order reduction for RLC/RC networks (NB, GA, WHAS, CT), pp. 1–6.
DATE-2014-BanerjeeD #calculus #constraints #generative #random #realtime #sequence
Acceptance and random generation of event sequences under real time calculus constraints (KB, PD), pp. 1–6.
DATE-2014-BardizbanyanSWL #data flow #dependence #detection #energy
Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3) (AB, MS, DBW, PLE), pp. 1–4.
DATE-2014-BartoliniCCTB #energy
Unveiling Eurora — Thermal and power characterization of the most energy-efficient supercomputer in the world (AB, MC, CC, GT, LB), pp. 1–6.
DATE-2014-Bautista-GomezCCDFGPRR #how #named #reliability
GPGPUs: How to combine high computational power with high reliability (LABG, FC, LC, ND, BF, SG, KP, PR, MSR), pp. 1–9.
DATE-2014-BeckerNI #named #sketching
SKETCHILOG: Sketching combinational circuits (AB, DN, PI), pp. 1–4.
DATE-2014-BelKKS #fault #multi
Improving STT-MRAM density through multibit error correction (BDB, JK, CHK, SSS), pp. 1–6.
DATE-2014-BeneventiBVDB #analysis #identification #logic
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip (FB, AB, PV, DD, LB), pp. 1–4.
DATE-2014-BeuxLOCLTN #named #performance
Chameleon: Channel efficient Optical Network-on-Chip (SLB, HL, IO, KC, XL, JT, GN), pp. 1–6.
DATE-2014-BhargavaM #encryption #generative #performance #reliability
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS (MB, KM), pp. 1–6.
DATE-2014-BhuniaRHRYMF #logic #towards
Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic (SB, VR, TH, SR, RY, MM, PXLF), pp. 1–6.
DATE-2014-BiewerGH #novel #smt
A novel model for system-level decision making with combined ASP and SMT solving (AB, JG, CH), pp. 1–4.
DATE-2014-BishnoiEOT #power management #symmetry #termination
Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM (RB, ME, FO, MBT), pp. 1–6.
DATE-2014-BoettcherAEGR #architecture
Advanced SIMD: Extending the reach of contemporary SIMD architectures (MB, BMAH, ME, GG, AR), pp. 1–4.
DATE-2014-Bolle #roadmap
The connected car and its implication to the automotive chip roadmap (MB), p. 1.
DATE-2014-BortolottiBWRB #architecture #hybrid #manycore #memory management #power management #scalability
Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors (DB, AB, CW, DR, LB), pp. 1–6.
DATE-2014-BournoutianO #framework #mobile #optimisation
On-device objective-C application optimization framework for high-performance mobile processors (GB, AO), pp. 1–6.
DATE-2014-Braak #adaptation #embedded #scalability #using
Using guided local search for adaptive resource reservation in large-scale embedded systems (TDtB), pp. 1–4.
DATE-2014-BraojosDBAA #approach #hardware #manycore #power management
Hardware/software approach for code synchronization in low-power multi-core sensor nodes (RB, AYD, IB, GA, DA), pp. 1–6.
DATE-2014-BurgioDMCB #clustering #hardware #programmable #scalability
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters (PB, RD, AM, PC, LB), pp. 1–4.
DATE-2014-BurgioTCMB #clustering #embedded #hardware #memory management #parallel
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters (PB, GT, FC, AM, LB), pp. 1–6.
DATE-2014-BurlyaevFG
Verification-guided voter minimization in triple-modular redundant circuits (DB, PF, AG), pp. 1–6.
DATE-2014-ButerOGO #configuration management #named
DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs (WB, CO, DG, AGO), pp. 1–4.
DATE-2014-ButtazzoBB #adaptation #analysis #design
Rate-adaptive tasks: Model, analysis, and design issues (GCB, EB, DB), pp. 1–6.
DATE-2014-CabodiPQV #approximate #reachability #satisfiability
Tightening BDD-based approximate reachability with SAT-based clause generalization∗ (GC, PP, SQ, DV), pp. 1–6.
DATE-2014-CanedoFR #automation #cyber-physical #design #multi
Multi-disciplinary integrated design automation tool for automotive cyber-physical systems (AC, MAAF, JHR), pp. 1–2.
DATE-2014-CannellaBS #approach #realtime #scheduling #streaming #using
System-level scheduling of real-time streaming applications using a semi-partitioned approach (EC, MB, TS), pp. 1–6.
DATE-2014-CaplanMMM #execution #reliability #trade-off
Trade-offs in execution signature compression for reliable processor systems (JC, MIM, PM, BHM), pp. 1–6.
DATE-2014-CasamassimaFB #network #power management
Context aware power management for motion-sensing body area network nodes (FC, EF, LB), pp. 1–6.
DATE-2014-CasparLH #automation #strict #testing #using
Automated system testing using dynamic and resource restricted clients (MC, ML, WH), pp. 1–4.
DATE-2014-CastellanaTF #adaptation #configuration management #hybrid #interface #memory management
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems (VGC, AT, FF), pp. 1–4.
DATE-2014-ChandraMCCM
Cross layer resiliency in real world (VC, SM, CYC, SMM), p. 1.
DATE-2014-ChangOSK #approximate #estimation #statistics
Approximating the age of RF/analog circuits through re-characterization and statistical estimation (DC, SO, OS, RK), pp. 1–4.
DATE-2014-ChenCH #array #configuration management #constraints #synthesis
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints (YHC, JYC, JDH), pp. 1–4.
DATE-2014-ChenCT #performance #simulation
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations (SYC, CHC, RST), pp. 1–6.
DATE-2014-ChenHD #analysis #graph #modelling
May-happen-in-parallel analysis based on segment graphs for safe ESL models (WC, XH, RD), pp. 1–6.
DATE-2014-ChenLLSHC #3d
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.
DATE-2014-ChenRC #adaptation #design #named #pipes and filters
DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors (HC, SR, KC), pp. 1–6.
DATE-2014-ChenTCC #effectiveness
Cost-effective decap selection for beyond die power integrity (YEC, THT, SHC, HMC), pp. 1–4.
DATE-2014-ChenWP #capacity #concurrent #distributed #framework
Concurrent placement, capacity provisioning, and request flow control for a distributed cloud infrastructure (SC, YW, MP), pp. 1–6.
DATE-2014-ChenZZ
Recovery-based resilient latency-insensitive systems (YC, XZ, HZ), pp. 1–6.
DATE-2014-ChienPWWLWW #cost analysis
Mask-cost-aware ECO routing∗ (HAC, ZYP, YRW, THW, HCL, CFW, TCW), pp. 1–4.
DATE-2014-ChienYHLC #analysis #geometry #image
Package geometric aware thermal analysis by infrared-radiation thermal images (JHC, HY, RSH, HJL, SCC), pp. 1–4.
DATE-2014-CilardoFGM #communication #manycore #scheduling #synthesis
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems (AC, EF, LG, AM), pp. 1–4.
DATE-2014-ClermidyJOOTTVPB #question
Resistive memories: Which applications? (FC, NJ, SO, HO, OT, OT, EV, JMP, MB), pp. 1–6.
DATE-2014-CongLYX #evaluation #prototype #testing #validation
Coverage evaluation of post-silicon validation tests with virtual prototypes (KC, LL, ZY, FX), pp. 1–6.
DATE-2014-ConosMDP #coordination #energy #power management #using
Provably minimal energy using coordinated DVS and power gating (NAC, SM, FD, MP), pp. 1–6.
DATE-2014-CortezRHN #testing
Testing PUF-based secure key storage circuits (MC, GR, SH, GDN), pp. 1–6.
DATE-2014-DamodaranWH #distributed #multi
Distributed cooperative shared last-level caching in tiled multiprocessor system on chip (PPD, SW, AH), pp. 1–4.
DATE-2014-DasKV #energy #multi #trade-off
Temperature aware energy-reliability trade-offs for mapping of throughput-constrained applications on multimedia MPSoCs (AD, AK, BV), pp. 1–6.
DATE-2014-DasKVBM
Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs (AD, AK, BV, CB, AM), pp. 1–6.
DATE-2014-DelvauxV
Key-recovery attacks on various RO PUF constructions via helper data manipulation (JD, IV), pp. 1–6.
DATE-2014-DhruvaKGT #cyber-physical
Computing a language-based guarantee for timing properties of cyber-physical systems (ND, PK, GG, LT), pp. 1–6.
DATE-2014-DijkR #protocol
Protocol attacks on advanced PUF protocols and countermeasures (MvD, UR), pp. 1–6.
DATE-2014-DimitrakopoulosSPTMC #hardware #parallel #synthesis #thread
Hardware primitives for the synthesis of multithreaded elastic systems (GD, IS, AP, KT, PMM, JC), pp. 1–4.
DATE-2014-DinechinAPL #parallel
Time-critical computing on a single-chip massively parallel processor (BDdD, DvA, MP, GL), pp. 1–6.
DATE-2014-DingLM
WCET-Centric dynamic instruction cache locking (HD, YL, TM), pp. 1–6.
DATE-2014-DinhYH #design #logic
A logic integrated optimal pin-count design for digital microfluidic biochips (TAD, SY, TYH), pp. 1–6.
DATE-2014-DoanJP #flexibility #implementation #multi #scalability #using
Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs (HCD, HJ, SP), pp. 1–6.
DATE-2014-DogaruSR #flexibility
A flexible BIST strategy for SDR transmitters (ED, FVdS, WR), pp. 1–6.
DATE-2014-DongZ #manycore #memory management #realtime #stack
Minimizing stack memory for hard real-time applications on multicore platforms (CD, HZ), pp. 1–6.
DATE-2014-DuanW
Exploiting narrow-width values for improving non-volatile cache lifetime (GD, SW), pp. 1–4.
DATE-2014-DuricPSUCVB #execution #named #power management
EVX: Vector execution on low power EDGE cores (MD, OP, AS, OSÜ, AC, MV, DB), pp. 1–4.
DATE-2014-DuW #optimisation #process #standard
Optimization of standard cell based detailed placement for 16 nm FinFET process (YD, MDFW), pp. 1–6.
DATE-2014-DweikAD #array #exception #fault
Reliability-Aware Exceptions: Tolerating intermittent faults in microprocessor array structures (WD, MA, MD), pp. 1–6.
DATE-2014-EbrahimiETSCA #analysis #embedded #fault
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales (ME, AE, MBT, RS, EC, DA), pp. 1–6.
DATE-2014-EckerVZG #approach #metamodelling #synthesis
The metamodeling approach to system level synthesis (WE, MV, LZ, AG), pp. 1–2.
DATE-2014-ErbSSB #fault #performance #smt
Efficient SMT-based ATPG for interconnect open defects (DE, KS, MS, BB), pp. 1–6.
DATE-2014-EusseLASLS #architecture #component #embedded #flexibility
A flexible ASIP architecture for connected components labeling in embedded vision applications (JFE, RL, GA, PS, BL, TS), pp. 1–6.
DATE-2014-FabrieEVG #design #library #standard #variability
Standard cell library tuning for variability tolerant designs (SF, JDE, MV, JPdG), pp. 1–6.
DATE-2014-FarbehM #architecture #fault tolerance #low cost #memory management #named
PSP-Cache: A low-cost fault-tolerant cache memory architecture (HF, SGM), pp. 1–4.
DATE-2014-FerentD #comparison #mining #novel #synthesis #using
Novel circuit topology synthesis method using circuit feature mining and symbolic comparison (CF, AD), pp. 1–4.
DATE-2014-FischerCM #analysis #design #modelling
Power modeling and analysis in early design phases (BF, CC, HM), pp. 1–6.
DATE-2014-FourmigueBN #3d #performance #simulation
Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias (AF, GB, GN), pp. 1–6.
DATE-2014-FrancillonNRT #approach
A minimalist approach to Remote Attestation (AF, QN, KBR, GT), pp. 1–6.
DATE-2014-FriedlerKMNS #effectiveness #locality #slicing #using
Effective post-silicon failure localization using dynamic program slicing (OF, WK, AM, AN, VS), pp. 1–6.
DATE-2014-FrijnsASVGSC #analysis #graph
Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs (RF, SA, SS, JV, MCWG, RRHS, HC), pp. 1–6.
DATE-2014-Fu0PJZ #data flow #detection #fault #parallel #thread
A fault detection mechanism in a Data-flow scheduled Multithreaded processor (JF, QY, RP, CRJ, CZ), pp. 1–4.
DATE-2014-Fuller #challenge #design #embedded #generative
System design challenges for next generation wireless and embedded systems (DF), p. 1.
DATE-2014-FummiLSTVV #design #effectiveness #simulation
Moving from co-simulation to simulation for effective smart systems design (FF, ML, FS, DT, JV, SV), pp. 1–4.
DATE-2014-GaillardonAZM #design
Advanced system on a chip design based on controllable-polarity FETs (PEG, LGA, JZ, GDM), pp. 1–6.
DATE-2014-GanapathyCACGR #analysis #framework #memory management #named #robust
INFORMER: An integrated framework for early-stage memory robustness analysis (SG, RC, DA, EC, AG, AR), pp. 1–4.
DATE-2014-GangopadhyayLNR #adaptation #analysis #linear #modelling #performance
Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads (SG, YL, SBN, AR), pp. 1–6.
DATE-2014-GaoGWP #energy #fault #fault tolerance #framework #in the cloud #scheduling
An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems (YG, SKG, YW, MP), pp. 1–6.
DATE-2014-GemmekeSSRCA #memory management
Resolving the memory bottleneck for single supply near-threshold computing (TG, MMS, JS, PR, FC, DA), pp. 1–6.
DATE-2014-GhalatyAS #analysis #fault
Analyzing and eliminating the causes of fault sensitivity analysis (NFG, AA, PS), pp. 1–6.
DATE-2014-GholipourCSC #modelling #scalability
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling (MG, YYC, AS, DC), pp. 1–6.
DATE-2014-GiannopoulouSHT #architecture #manycore
Mapping mixed-criticality applications on multi-core architectures (GG, NS, PH, LT), pp. 1–6.
DATE-2014-GinesL #pipes and filters #testing
Sigma-delta testability for pipeline A/D converters (AJG, GL), pp. 1–6.
DATE-2014-GomonyAG #optimisation #performance #realtime
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems (MDG, BA, KG), pp. 1–6.
DATE-2014-GrafGTL #design #embedded #multi
Multi-variant-based design space exploration for automotive embedded systems (SG, MG, JT, CL), pp. 1–6.
DATE-2014-Guan0 #analysis #performance #scheduling
General and efficient Response Time Analysis for EDF scheduling (NG, WY), pp. 1–6.
DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification
A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
DATE-2014-GuerreAL #architecture #benchmark #metric #parallel #performance
A unified methodology for a fast benchmarking of parallel architecture (AG, JTA, YL), pp. 1–4.
DATE-2014-GuGD0 #multi #scheduling
Partitioned mixed-criticality scheduling on multiprocessor platforms (CG, NG, QD, WY), pp. 1–6.
DATE-2014-GuoWWH #automation #effectiveness #named #test coverage
EATBit: Effective automated test for binary translation with high code coverage (HG, ZW, CW, RH), pp. 1–6.
DATE-2014-HaddadTBF #independence #modelling #on the #probability
On the assumption of mutual independence of jitter realizations in P-TRNG stochastic models (PH, YT, FB, VF), pp. 1–6.
DATE-2014-HamdiouiDNSBT #hardware
Hacking and protecting IC hardware (SH, JLD, GDN, FS, GvB, MT), pp. 1–7.
DATE-2014-HanKNV #learning
A deep learning methodology to proliferate golden signoff timing (SSH, ABK, SN, ASV), pp. 1–6.
DATE-2014-HanZLD #named #scheduling
SAFE: Security-Aware FlexRay Scheduling Engine (GH, HZ, YL, WD), pp. 1–4.
DATE-2014-HaoRX #behaviour #equivalence #pipes and filters #synthesis
Equivalence checking for function pipelining in behavioral synthesis (KH, SR, FX), pp. 1–6.
DATE-2014-HarrantNKGP #assessment #robust
Emulation-based robustness assessment for automotive smart-power ICs (MH, TN, JK, CG, GP), pp. 1–6.
DATE-2014-HeidmannHHWPP #design #modelling
Modeling of an analog recording system design for ECoG and AP signals (NH, NH, TH, TW, DPD, SP), pp. 1–6.
DATE-2014-HeinigDHMWHGBKR #integration
System integration — The bridge between More than Moore and More Moore (AH, MD, AH, FM, TW, KH, AG, RB, SK, JR), pp. 1–9.
DATE-2014-HelfmeierBNTS #physics
Physical vulnerabilities of Physically Unclonable Functions (CH, CB, DN, ST, JPS), pp. 1–4.
DATE-2014-HenselK #energy
The energy benefit of level-crossing sampling including the actuator’s energy consumption (BH, KK), pp. 1–4.
DATE-2014-HeYH0 #design #named #power management
SuperRange: Wide operational range power delivery design for both STV and NTV computing (XH, GY, YH, XL), pp. 1–6.
DATE-2014-HillerS #performance
Increasing the efficiency of syndrome coding for PUFs with helper data compression (MH, GS), pp. 1–6.
DATE-2014-HoffmanRAA #analysis #fault #memory management
Wear-out analysis of Error Correction Techniques in Phase-Change Memory (CH, LR, RA, GA), pp. 1–4.
DATE-2014-HsuCMGB #architecture #named #performance #validation
ArChiVED: Architectural checking via event digests for high performance validation (CHH, DC, RM, RG, VB), pp. 1–6.
DATE-2014-Huang #performance
A high performance SEU-tolerant latch for nanoscale CMOS technology (ZH), pp. 1–5.
DATE-2014-Huang14a #manycore #network #performance #predict
Leveraging on-chip networks for efficient prediction on multicore coherence (LH), pp. 1–4.
DATE-2014-IannopolloNTS #contract #design #refinement #scalability
Library-based scalable refinement checking for contract-based design (AI, PN, ST, ALSV), pp. 1–6.
DATE-2014-IliasovASM #design #refinement #safety
Design of safety critical systems by refinement (AI, AA, DS, AM), pp. 1–4.
DATE-2014-ImhofW #architecture #fault tolerance
Bit-Flipping Scan — A unified architecture for fault tolerance and offline test (MEI, HJW), pp. 1–6.
DATE-2014-IvanovPL
Attack-resilient sensor fusion (RI, MP, IL), pp. 1–6.
DATE-2014-JaksicC #energy #how #protocol
DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy (ZJ, RC), pp. 1–4.
DATE-2014-JalleKAQC #design #manycore
Bus designs for time-probabilistic multicore processors (JJ, LK, JA, EQ, FJC), pp. 1–6.
DATE-2014-JeongOSNS #parametricity #self
Built-in self-test and characterization of polar transmitter parameters in the loop-back mode (JWJ, SO, SS, VN, MS), pp. 1–6.
DATE-2014-JerkeK #case study #design
Mission profile aware IC design — A case study (GJ, ABK), pp. 1–6.
DATE-2014-Jin #evaluation #proving #security #tool support #trust
EDA tools trust evaluation through security property proofs (YJ), pp. 1–4.
DATE-2014-JinS #evaluation #realtime #trust
Real-time trust evaluation in integrated circuits (YJ, DS), pp. 1–6.
DATE-2014-JonnaJRM
Minimally buffered single-cycle deflection router (GRJ, JJ, RR, MM), pp. 1–4.
DATE-2014-JoostenS #communication #liveness #scalability #verification
Scalable liveness verification for communication fabrics (SJCJ, JS), pp. 1–6.
DATE-2014-JunsangsriLH #concurrent #detection #hybrid
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction (PJ, FL, JH), pp. 1–4.
DATE-2014-KahngK #logic #memory management #scheduling
Co-optimization of memory BIST grouping, test scheduling, and logic placement (ABK, IK), pp. 1–6.
DATE-2014-KamalGAP #approximate #performance #using
Improving efficiency of extensible processors by using approximate custom instructions (MK, AG, AAK, MP), pp. 1–4.
DATE-2014-KangYKBHT #manycore #optimisation
Reliability-aware mapping optimization of multi-core systems with mixed-criticality (SHK, HY, SK, IB, SH, LT), pp. 1–4.
DATE-2014-KarakonstantisSSAB #analysis #approach #energy #variability
A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability (GK, AS, MMS, DA, AB), pp. 1–6.
DATE-2014-KarkarDATMY #architecture #communication #hybrid
Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip (AK, ND, RAD, KT, TSTM, AY), pp. 1–4.
DATE-2014-KarlssonF
Thinfilm printed ferro-electric memories and integrated products (CK, PF), p. 1.
DATE-2014-KatzschkeSOBTB #constraints #design
Application of Mission Profiles to enable cross-domain constraint-driven design (CK, MPS, MO, VMzB, MT, EB), pp. 1–6.
DATE-2014-KauerSGCA #distributed #embedded #fault tolerance #synthesis #verification
Fault-tolerant control synthesis and verification of distributed embedded systems (MK, DS, DG, SC, AMA), pp. 1–6.
DATE-2014-KeramidasMKN #predict
Spatial pattern prediction based management of faulty data caches (GK, MM, AK, DN), pp. 1–6.
DATE-2014-KhanAHKKRC #analysis #bias
Bias Temperature Instability analysis of FinFET based SRAM cells (SK, IA, SH, HK, BK, PR, FC), pp. 1–6.
DATE-2014-KhanSH #architecture #manycore #performance #power management #video
Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing (MUKK, MS, JH), pp. 1–6.
DATE-2014-KhdrESAH #multi #named
mDTM: Multi-objective dynamic thermal management for on-chip systems (HK, TE, MS, HA, JH), pp. 1–6.
DATE-2014-KiamehrFET #design #library #standard
Aging-aware standard cell library design (SK, FF, ME, MBT), pp. 1–4.
DATE-2014-KimH #automation #generative #parallel
Automatic generation of custom SIMD instructions for Superword Level Parallelism (TK, YH), pp. 1–6.
DATE-2014-KimHPSL #approach #implementation #modelling #testing
A layered approach for testing timing in the model-based implementation (BK, HIH, TP, SHS, IL), pp. 1–4.
DATE-2014-KimKGH #energy #performance
Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processor (MK, KK, JRG, SH), pp. 1–4.
DATE-2014-KimKKYL #design
Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs (HK, DK, JJK, SY, SL), pp. 1–6.
DATE-2014-KimSAVG #enterprise #metric
Global fan speed control considering non-ideal temperature measurements in enterprise servers (JK, MMS, DA, KV, KCG), pp. 1–6.
DATE-2014-KimSXWPC #android #fine-grained #monitoring #named #smarttech
FEPMA: Fine-grained event-driven power meter for android smartphones based on device driver layer event monitoring (KK, DS, QX, YW, MP, NC), pp. 1–6.
DATE-2014-KomalanPTRHC
Feasibility exploration of NVM based I-cache through MSHR enhancements (MK, JIGP, CT, PR, MH, FC), pp. 1–6.
DATE-2014-KondoKSWTNWAMKUKN #design #embedded #evaluation #fine-grained
Design and evaluation of fine-grained power-gating for embedded microprocessors (MK, HK, RS, MW, JT, MN, WW, HA, KM, MK, KU, TK, HN), pp. 1–6.
DATE-2014-KordesVDW #detection #fault #hybrid #network #robust
Startup error detection and containment to improve the robustness of hybrid FlexRay networks (AK, BV, AKD, MGW), pp. 1–6.
DATE-2014-KoundinyaTFPBS #multi
Multi resolution touch panel with built-in fingerprint sensing support (PK, ST, TF, VP, JB, WS), pp. 1–6.
DATE-2014-Kreupl
Advancing CMOS with carbon electronics (FK), pp. 1–6.
DATE-2014-KufelWHAWM #embedded
Clock-modulation based watermark for protection of embedded processors (JK, PRW, SH, BMAH, PNW, JM), pp. 1–6.
DATE-2014-KumarYBT #distributed #effectiveness #named
COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors (PK, HY, IB, LT), pp. 1–4.
DATE-2014-LagraaTP #data mining #mining #scalability #simulation #using
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces (SL, AT, FP), pp. 1–6.
DATE-2014-LamWCHHPZ #garbage collection #memory management #multi
Garbage collection for multi-version index on flash memory (KyL, JW, YHC, JWH, PCH, CKP, CJZ), pp. 1–4.
DATE-2014-LangeSJHLS #correlation #modelling #parametricity #probability #standard
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations (AL, CS, RJ, JH, IL, US), pp. 1–4.
DATE-2014-Lauwereins
Interfacing to living cells (RL), pp. 1–3.
DATE-2014-LeD #design #towards #verification
Towards verifying determinism of SystemC designs (HML, RD), pp. 1–4.
DATE-2014-LeeA #architecture #hybrid #novel #power management #using
A novel low power 11-bit hybrid ADC using flash and delay line architectures (HCL, JAA), pp. 1–4.
DATE-2014-LeeF #framework #named #realtime #runtime #scheduling
GPU-EvR: Run-time event based real-time scheduling framework on GPGPU platform (HL, MAAF), pp. 1–6.
DATE-2014-LeeL #3d #gpu #on the #reduction
On GPU bus power reduction with 3D IC technologies (YJL, SKL), pp. 1–6.
DATE-2014-LeeLC
Design-for-debug routing for FIB probing (CYL, THL, TCC), pp. 1–4.
DATE-2014-LeePB #configuration management
Brisk and limited-impact NoC routing reconfiguration (DL, RP, VB), pp. 1–6.
DATE-2014-LeeserMRW #effectiveness #float #reasoning
Make it real: Effective floating-point reasoning via exact arithmetic (ML, SM, JR, TW), pp. 1–4.
DATE-2014-LeeWP #configuration management #framework #manycore #named
VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform (WL, YW, MP), pp. 1–6.
DATE-2014-Leo
Organic electronics — From lab to markets (KL), p. 1.
DATE-2014-LeupersWLRSFCJ #towards
Technology transfer towards Horizon 2020 (RL, NW, RL, MR, JS, LF, AC, BJ), p. 1.
DATE-2014-LiHCXJX #embedded #memory management #stack
A wear-leveling-aware dynamic stack for PCM memory in embedded systems (QL, YH, YC, CJX, NJ, CX), pp. 1–4.
DATE-2014-LiM #memory management
Write-once-memory-code phase change memory (JL, KM), pp. 1–6.
DATE-2014-LinWCH #logic
Rewiring for threshold logic circuit minimization (CCL, CYW, YCC, CYH), pp. 1–6.
DATE-2014-LinZH #low cost
A low-cost radiation hardened flip-flop (YL, MZ, BH), pp. 1–6.
DATE-2014-LiSH0 #in memory #memory management #named
Partial-SET: Write speedup of PCM main memory (BL, SS, YH, XL), pp. 1–4.
DATE-2014-LiuBC #hardware #image
Image progressive acquisition for hardware systems (JL, CSB, PYKC), pp. 1–6.
DATE-2014-LiuCHWCDN #array #synthesis
Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
DATE-2014-LiuCW
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost (WHL, TKC, TCW), pp. 1–6.
DATE-2014-LiuHL #approximate #configuration management #fault #multi #power management
A low-power, high-performance approximate multiplier with configurable partial error recovery (CL, JH, FL), pp. 1–4.
DATE-2014-LiuJL #parallel
Parallel probe based dynamic connection setup in TDM NoCs (SL, AJ, ZL), pp. 1–6.
DATE-2014-LiuSXL #injection #programmable #thread
Programmable decoder and shadow threads: Tolerate remote code injection exploits with diversified redundancy (ZL, WS, SX, ZL), pp. 1–6.
DATE-2014-LiuSZSC #constraints #latency #optimisation #streaming
Resource optimization for CSDF-modeled streaming applications with latency constraints (DL, JS, JTZ, TS, GC), pp. 1–6.
DATE-2014-LiuW #configuration management #design #embedded #logic #obfuscation
Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks (BL, BW), pp. 1–6.
DATE-2014-LiWCLY #named
ICE: Inline calibration for memristor crossbar-based computing engine (BL, YW, YC, HHL, HY), pp. 1–4.
DATE-2014-LoiB #multi
A multi banked — Multi ported — Non blocking shared L2 cache for MPSoC platforms (IL, LB), pp. 1–6.
DATE-2014-LongLY #analysis #bound #evaluation #modelling #multi
Analysis and evaluation of per-flow delay bound for multiplexing models (YL, ZL, XY), pp. 1–4.
DATE-2014-LuCC #correlation #memory management #performance
Achieving efficient packet-based memory system by exploiting correlation of memory requests (TL, LC, MC), pp. 1–6.
DATE-2014-MacrelliWRHPTR #design #energy
Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvesting (EM, NW, SR, MH, RPP, MT, AR), pp. 1–4.
DATE-2014-MahmoodPM #performance #reduction #using
Cache aging reduction with improved performance using dynamically re-sizable cache (HM, MP, EM), pp. 1–6.
DATE-2014-MaliukM #framework #network #prototype
An analog non-volatile neural network platform for prototyping RF BIST solutions (DM, YM), pp. 1–6.
DATE-2014-MarianiPZS #design #named #predict #scheduling #simulation #using
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling (GM, GP, VZ, CS), pp. 1–4.
DATE-2014-Matsunaga #algorithm #generative #parallel #synthesis
Synthesis algorithm of parallel index generation units (YM), pp. 1–6.
DATE-2014-MatsutaniKFKTKBMA #3d #random
Low-latency wireless 3D NoCs via randomized shortcut chips (HM, MK, IF, TK, YT, TK, PB, RM, HA), pp. 1–6.
DATE-2014-Maurer #algorithm #detection #symmetry
A universal symmetry detection algorithm (PMM), pp. 1–4.
DATE-2014-MaurichG #configuration management #encryption #lightweight
Lightweight code-based cryptography: QC-MDPC McEliece encryption on reconfigurable devices (IvM, TG), pp. 1–6.
DATE-2014-MeeusS #automation #reuse #synthesis
Automating data reuse in High-Level Synthesis (WM, DS), pp. 1–4.
DATE-2014-MembarthRHT #android #architecture #code generation #embedded
Code generation for embedded heterogeneous architectures on android (RM, OR, FH, JT), pp. 1–6.
DATE-2014-MercatiBPRB #android #mobile #reliability
A Linux-governor based Dynamic Reliability Manager for android mobile devices (PM, AB, FP, TSR, LB), pp. 1–4.
DATE-2014-MineoPAC #adaptation #energy #performance
An adaptive transmitting power technique for energy efficient mm-wave wireless NoCs (AM, MP, GA, VC), pp. 1–6.
DATE-2014-MooreC #modelling #performance
Program affinity performance models for performance and utilization (RWM, BRC), pp. 1–4.
DATE-2014-MoralesHBHV #energy #implementation #using
Energy-efficient FPGA implementation for binomial option pricing using OpenCL (VMM, PHH, AB, EH, SV), pp. 1–6.
DATE-2014-MottaghiRD #framework #named #network #performance
RETLab: A fast design-automation framework for arbitrary RET networks (MDM, AR, CD), pp. 1–6.
DATE-2014-MullerM #scheduling
The schedulability region of two-level mixed-criticality systems based on EDF-VD (DM, AM), pp. 1–6.
DATE-2014-MunirK #automation #design #named
D2Cyber: A design automation tool for dependable cybercars (AM, FK), pp. 1–4.
DATE-2014-MurilloWCLA #automation #concurrent #constraints #debugging #detection
Automatic detection of concurrency bugs through event ordering constraints (LGM, SW, JC, RL, GA), pp. 1–6.
DATE-2014-NaqviS #resource management
A tree arbiter cell for high speed resource sharing in asynchronous environments (SRN, AS), pp. 1–6.
DATE-2014-NarayananDCCLW #using #video
Video analytics using beyond CMOS devices (VN, SD, GC, DMC, SPL, PW), pp. 1–5.
DATE-2014-NarayanaswamySLKC #architecture
Optimal dimensioning of active cell balancing architectures (SN, SS, ML, MK, SC), pp. 1–6.
DATE-2014-NathanS #detection #fault #low cost #named
Nostradamus: Low-cost hardware-only error detection for processor cores (RN, DJS), pp. 1–6.
DATE-2014-NawinneSJP #performance
Hardware-based fast exploration of cache hierarchies in application specific MPSoCs (IN, JS, HJ, SP), pp. 1–6.
DATE-2014-NejatAA #power management #process
Dynamic Flip-Flop conversion to tolerate process variation in low power circuits (MN, BA, AAK), pp. 1–4.
DATE-2014-NelsonNMKG #composition #kernel #named #predict #realtime
CoMik: A predictable and cycle-accurately composable real-time microkernel (AN, ABN, AMM, MK, KG), pp. 1–4.
DATE-2014-NepalLBR #approximate #automation #behaviour #named #synthesis
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits (KN, YL, RIB, SR), pp. 1–6.
DATE-2014-NikitakisPP #embedded #novel
A novel embedded system for vision tracking (AN, TP, IP), pp. 1–4.
DATE-2014-NirmaierBHVBRP #assessment #robust
Mission profile aware robustness assessment of automotive power devices (TN, AB, MH, AV, OB, WR, GP), pp. 1–6.
DATE-2014-NoursPB #architecture #evaluation #manycore #performance
A dynamic computation method for fast and accurate performance evaluation of multi-core architectures (SLN, AP, NWB), pp. 1–6.
DATE-2014-NovoFIAC #approximate #case study #energy #performance #runtime
Energy efficient MIMO processing: A case study of opportunistic run-time approximations (DN, NF, PI, UA, FC), pp. 1–6.
DATE-2014-NowotschPHPS #analysis #monitoring #multi #off the shelf
Monitoring and WCET analysis in COTS multi-core-SoC-based mixed-criticality systems (JN, MP, AH, WP, AS), pp. 1–5.
DATE-2014-NuzzoFIS #contract #cyber-physical #design #protocol #safety
Contract-based design of control protocols for safety-critical cyber-physical systems (PN, JBF, AI, ALSV), pp. 1–4.
DATE-2014-OdendahlGLARVH #manycore
Optimized buffer allocation in multicore platforms (MO, AG, RL, GA, BR, BV, TH), pp. 1–6.
DATE-2014-OrtinGVIV
Dynamic construction of circuits for reactive traffic in homogeneous CMPs (MO, DSG, MV, CI, VV), pp. 1–4.
DATE-2014-PalerDNP #fault tolerance #quantum
Software-based Pauli tracking in fault-tolerant quantum circuits (AP, SJD, KN, IP), pp. 1–4.
DATE-2014-PalitSHHNN #architecture #case study
Impact of steep-slope transistors on non-von Neumann architectures: CNN case study (IP, BS, AH, XSH, JN, MTN), pp. 1–6.
DATE-2014-PalominoSASH #named #performance #video
hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding (DP, MS, HA, AAS, JH), pp. 1–4.
DATE-2014-PandaB #concurrent #thread
Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control (BP, SB), pp. 1–6.
DATE-2014-PandeyV #analysis #fault #safety
Transient errors resiliency analysis technique for automotive safety critical applications (SP, BV), pp. 1–4.
DATE-2014-PapadimitriouHBML #clustering #fault #injection #modelling #multi #towards
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks (AP, DH, VB, PM, RL), pp. 1–4.
DATE-2014-ParkKK #design #multi #synthesis
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.
DATE-2014-ParkYLL #graph #memory management #representation
Accelerating graph computation with racetrack memory and pointer-assisted graph representation (EP, SY, SL, HL), pp. 1–4.
DATE-2014-PaternaZR #component #mobile
Ambient variation-tolerant and inter components aware thermal management for mobile system on chips (FP, JZ, TSR), pp. 1–6.
DATE-2014-PaulKBP #energy #hardware #memory management
Energy-efficient hardware acceleration through computing in the memory (SP, RK, SB, RP), pp. 1–6.
DATE-2014-PerriconeHNN #3d #case study #design #logic
Design of 3D nanomagnetic logic circuits: A full-adder case study (RP, XSH, JN, MTN), pp. 1–6.
DATE-2014-Pomeranz #generative #testing
Test and non-test cubes for diagnostic test generation based on merging of test cubes (IP), pp. 1–4.
DATE-2014-Pomeranz14a #fault
Substituting transition faults with path delay faults as a basic delay fault model (IP), pp. 1–6.
DATE-2014-PrenatPLGJDSPN #logic #power management
Magnetic memories: From DRAM replacement to ultra low power logic chips (GP, GdP, CL, OG, KJ, BD, RCS, ILP, JPN), p. 1.
DATE-2014-PuEMG #logic #power management #scalability #synthesis
Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
DATE-2014-QiZ #modelling #performance #simulation
Efficient simulation and modelling of non-rectangular NoC topologies (JQ, MZ), pp. 1–4.
DATE-2014-RadojicicGMP #analysis
Semi-symbolic analysis of mixed-signal systems including discontinuities (CR, CG, JM, XP), pp. 1–4.
DATE-2014-RahimiBG #energy #fault
Temporal memoization for energy-efficient timing error recovery in GPGPUs (AR, LB, RKG), pp. 1–6.
DATE-2014-RahmanFFT #design #named
ARO-PUF: An aging-resistant ring oscillator PUF design (MTR, DF, JF, MT), pp. 1–6.
DATE-2014-RamboTDAE #analysis #realtime
Failure analysis of a network-on-chip for real-time mixed-critical systems (EAR, AT, JD, LA, RE), pp. 1–4.
DATE-2014-RaminiGGBFB #architecture #energy
Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline (LR, AG, PG, SB, HTF, DB), pp. 1–6.
DATE-2014-RanaC #analysis #named #reduction #scalability #simulation
SSFB: A highly-efficient and scalable simulation reduction technique for SRAM yield analysis (MR, RC), pp. 1–6.
DATE-2014-RanjanRVRR #approximate #named #synthesis
ASLAN: Synthesis of approximate sequential circuits (AR, AR, SV, KR, AR), pp. 1–6.
DATE-2014-RehmanKSH #compilation #reliability
Compiler-driven dynamic reliability management for on-chip systems under variabilities (SR, FK, MS, JH), pp. 1–4.
DATE-2014-ReimerSSB #using
Using MaxBMC for Pareto-optimal circuit initialization (SR, MS, TS, BB), pp. 1–6.
DATE-2014-ReinekeW #performance #predict #resource management
Impact of resource sharing on performance and performance prediction (JR, RW), pp. 1–2.
DATE-2014-RichterVSHV #challenge
Integrated circuits processing chemical information: Prospects and challenges (AR, AV, RS, SH, MV), p. 1.
DATE-2014-RiefertCSBRB #approach #automation #effectiveness #fault #functional #generative #testing
An effective approach to automatic functional processor test generation for small-delay faults (AR, LMC, MS, PB, MSR, BB), pp. 1–6.
DATE-2014-RobinoO
From Simulink to NoC-based MPSoC on FPGA (FR, ), pp. 1–4.
DATE-2014-RossiTB #hybrid #optimisation #realtime
Real-time optimization of the battery banks lifetime in Hybrid Residential Electrical Systems (MR, AT, DB), pp. 1–6.
DATE-2014-RostamiWPK #challenge #roadmap #security
Quo vadis, PUF?: Trends and challenges of emerging physical-disorder based security (MR, JBW, MP, FK), pp. 1–6.
DATE-2014-RosvallS #constraints #design #framework #realtime
A constraint-based design space exploration framework for real-time applications on MPSoCs (KR, IS), pp. 1–6.
DATE-2014-RoyJ #named #optimisation #thread
ALLARM: Optimizing sparse directories for thread-local data (AR, TMJ), pp. 1–6.
DATE-2014-RoySFY
Brain-inspired computing with spin torque devices (KR, MS, DF, KY), pp. 1–6.
DATE-2014-RuhrmairH
PUFs at a glance (UR, DEH), pp. 1–6.
DATE-2014-RuhrmairS #bibliography #modelling #perspective
PUF modeling attacks: An introduction and overview (UR, JS), pp. 1–6.
DATE-2014-RuhrmairSB #how
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks (UR, US, WB), pp. 1–4.
DATE-2014-SabrySARM #generative
Integrated microfluidic power generation and cooling for bright silicon MPSoCs (MMS, AS, DA, PR, BM), pp. 1–6.
DATE-2014-Sadri0WWB #3d #energy #optimisation #using
Energy optimization in 3D MPSoCs with Wide-I/O DRAM using temperature variation aware bank-wise refresh (MS, MJ, CW, NW, LB), pp. 1–4.
DATE-2014-SalunkheMB #analysis #data flow #modelling
Mode-Controlled Dataflow based modeling & analysis of a 4G-LTE receiver (HS, OM, KvB), pp. 1–4.
DATE-2014-SampaioSZBH #architecture #distributed #energy #memory management #named #performance #video
dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding (FS, MS, BZ, SB, JH), pp. 1–6.
DATE-2014-SanderSDBBBMKALHRHH #hardware #manycore
Hardware virtualization support for shared resources in mixed-criticality multicore systems (OS, TS, VVD, SB, FB, JB, HUM, DK, DA, EL, JH, AR, CH, AH), pp. 1–6.
DATE-2014-SarafBLR #probability #using
IIR filters using stochastic arithmetic (NS, KB, DJL, MDR), pp. 1–6.
DATE-2014-SarmaD #estimation #network #runtime
Minimal sparse observability of complex networks: Application to MPSoC sensor placement and run-time thermal estimation & tracking (SS, ND), pp. 1–6.
DATE-2014-SassolasSGAVBFP #architecture #design #evaluation
Early design stage thermal evaluation and mitigation: The locomotiv architectural case (TS, CS, AG, AA, PV, HB, LF, NP), pp. 1–2.
DATE-2014-SchlichtmannKAEGGHNW #abstraction #design
Connecting different worlds — Technology abstraction for reliability-aware design and Test (US, VK, JAA, AE, CGD, MG, AH, SRN, NW), pp. 1–8.
DATE-2014-SchmidBMKSKMSR
III-V semiconductor nanowires for future devices (HS, BMB, KM, PDK, GS, SFK, PM, VS, HR), pp. 1–2.
DATE-2014-SchollPDA #linear
Simple interpolants for linear arithmetic (CS, FP, SD, EA), pp. 1–6.
DATE-2014-SchollW #hardware #implementation #set
Hardware implementation of a Reed-Solomon soft decoder based on information set decoding (SS, NW), pp. 1–6.
DATE-2014-SeidlK #quantifier
Partial witnesses from preprocessed quantified Boolean formulas (MS, RK), pp. 1–6.
DATE-2014-SeitanidisPDN #architecture #named
ElastiStore: An elastic buffer architecture for Network-on-Chip routers (IS, AP, GD, CN), pp. 1–6.
DATE-2014-SeylerSWSGT #network #self
A self-propagating wakeup mechanism for point-to-point networks with partial network support (JRS, TS, JW, MS, MG, JT), pp. 1–6.
DATE-2014-ShangZXY #design
Asynchronous design for new on-chip wide dynamic range power electronics (DS, XZ, FX, AY), pp. 1–6.
DATE-2014-SharmaPLAC #composition #data flow #energy #performance
Energy efficient data flow transformation for Givens Rotation based QR Decomposition (NS, PRP, ML, PA, FC), pp. 1–4.
DATE-2014-ShenCQ #mobile #probability
Battery aware stochastic QoS boosting in mobile computing devices (HS, QC, QQ), pp. 1–4.
DATE-2014-ShenQ #quality #scalability
Contention aware frequency scaling on CMPs with guaranteed quality of service (HS, QQ), pp. 1–6.
DATE-2014-ShiC #named
Memcomputing: The cape of good hope: [Extended special session description] (YS, HMC), pp. 1–3.
DATE-2014-ShinPM #architecture #hybrid #using
Thermal management of batteries using a hybrid supercapacitor architecture (DS, MP, EM), pp. 1–6.
DATE-2014-SiddiqueT #analysis #formal method #towards
Towards the formal analysis of microresonators based photonic systems (US, ST), pp. 1–6.
DATE-2014-SilvaLCH #multi
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures (RMAeS, NCL, AC, NH), pp. 1–6.
DATE-2014-SilvanoPXS #architecture #manycore
Voltage island management in near threshold manycore architectures to mitigate dark silicon (CS, GP, SX, ISS), pp. 1–6.
DATE-2014-SinghSWPWC #analysis #specification
Cross-correlation of specification and RTL for soft IP analysis (BPS, AS, FGW, CAP, DJW, SC), pp. 1–6.
DATE-2014-SongDY #analysis #bound #multi #order #parametricity #performance #reduction
Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations (YS, SMPD, HY), pp. 1–6.
DATE-2014-SongLKSCR #energy #scheduling
Energy-efficient scheduling for memory-intensive GPGPU workloads (SS, ML, JK, WS, YGC, SR), pp. 1–6.
DATE-2014-Stenstrom #effectiveness #performance #resource management #towards
Effective resource management towards efficient computing (PS), p. 1.
DATE-2014-SubramanyanA #design #security #verification
Formal verification of taint-propagation security properties in a commercial SoC design (PS, DA), pp. 1–2.
DATE-2014-SunMSPL #design #power management #robust
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance (LS, JM, RAS, DKP, ZL), pp. 1–4.
DATE-2014-SwaminathanKCSPSN #architecture #modelling
Modeling steep slope devices: From circuits to architectures (KS, MSK, NC, BS, RP, JS, VN), pp. 1–6.
DATE-2014-TangZS #design #development #performance
System-level design methodology enabling fast development of baseband MP-SoC for 4G small cell base station (ST, ZZ, YS), pp. 1–6.
DATE-2014-TaouilMHM #3d
Interconnect test for 3D stacked memory-on-logic (MT, MM, SH, EJM), pp. 1–6.
DATE-2014-Taylor #design
A landscape of the new dark silicon design regime (MBT), p. 1.
DATE-2014-Teepe #perspective
The growing importance of microelectronics from a foundry perspective (GT), p. 1.
DATE-2014-TenaceCMP #logic
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits (VT, AC, EM, MP), pp. 1–4.
DATE-2014-Thanner #lifecycle #prototype
Virtual prototype life cycle in automotive applications (MT), p. 1.
DATE-2014-Torrellas #architecture #energy #performance
Extreme-scale computer architecture: Energy efficiency from the ground up‡ (JT), pp. 1–5.
DATE-2014-TrivediAM #power management
Ultra-low power electronics with Si/Ge tunnel FET (ART, MFA, SM), pp. 1–6.
DATE-2014-TsaiCCC #3d #configuration management #memory management #multi
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs (MLT, YJC, YTC, RHC), pp. 1–6.
DATE-2014-TsoutsosM #named
HEROIC: Homomorphically EncRypted One Instruction Computer (NGT, MM), pp. 1–6.
DATE-2014-TtofisT #hardware #image #realtime
High-quality real-time hardware stereo matching based on guided image filtering (CT, TT), pp. 1–6.
DATE-2014-TurkyilmazCRBC #3d #integration #using
3D FPGA using high-density interconnect Monolithic Integration (OT, GC, OR, PB, FC), pp. 1–4.
DATE-2014-UbolliGBC #linear #megamodelling
Sensitivity-based weighting for passivity enforcement of linear macromodels in power integrity applications (AU, SGT, MB, AC), pp. 1–6.
DATE-2014-VartziotisKCPJ #multi #optimisation #using
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing (FV, XK, KC, RAP, AJ), pp. 1–6.
DATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance
Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
DATE-2014-VenkateshSKA #named #specification
EDT: A specification notation for reactive systems (RV, US, GMK, SA), pp. 1–6.
DATE-2014-VijaykumarV #analysis #canonical #statistics #using
Statistical static timing analysis using a skew-normal canonical delay model (MV, VV), pp. 1–6.
DATE-2014-VillenaS #analysis #network #performance #variability
Efficient analysis of variability impact on interconnect lines and resistor networks (JFV, LMS), pp. 1–6.
DATE-2014-WangFOT #3d #reduction
P/G TSV planning for IR-drop reduction in 3D-ICs (SW, FF, FO, MBT), pp. 1–6.
DATE-2014-WangLLW0 #design #functional #generative #testing
Functional test generation guided by steady-state probabilities of abstract design (JW, HL, TL, TW, XL), pp. 1–4.
DATE-2014-WangLS #named #parallel #semantics
p-OFTL: An object-based semantic-aware parallel flash translation layer (WW, YL, JS), pp. 1–6.
DATE-2014-WangLXCP #energy #hybrid
Minimizing state-of-health degradation in hybrid electrical energy storage systems with arbitrary source and load profiles (YW, XL, QX, NC, MP), pp. 1–4.
DATE-2014-WangXWCWW #manycore #power management
Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATE-2014-WangYSK #encryption #energy #in memory #performance
Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire (YW, HY, DS, PK), pp. 1–4.
DATE-2014-WangZMYJDP #adaptation #manycore
Adaptive power allocation for many-core systems inspired from multiagent auction model (XW, BZ, TSTM, MY, YJ, MD, MP), pp. 1–4.
DATE-2014-WanK #embedded
An embedded offset and gain instrument for OpAmp IPs (JW, HGK), pp. 1–4.
DATE-2014-WeberTGHKM #challenge #configuration management
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges (WMW, JT, MG, AH, MK, TM), pp. 1–6.
DATE-2014-WeinstockSLAT #parallel #simulation
Time-decoupled parallel SystemC simulation (JHW, CS, RL, GA, LT), pp. 1–4.
DATE-2014-WelpK #invariant #refinement #verification
Property directed invariant refinement for program verification (TW, AK), pp. 1–6.
DATE-2014-WettinMKYPH #evaluation #network #performance
Performance evaluation of wireless NoCs in presence of irregular network routing strategies (PW, JM, RK, XY, PPP, DHH), pp. 1–6.
DATE-2014-WildermannGT #distributed #multi #resource management #runtime
Multi-objective distributed run-time resource management for many-cores (SW, MG, JT), pp. 1–6.
DATE-2014-Wuttig
Exploring the limits of phase change memories (MW), pp. 1–2.
DATE-2014-WuWDHYY #in memory #integration #manycore #memory management
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os (SSW, KW, SMPD, TYH, MY, HY), pp. 1–4.
DATE-2014-XuB #hybrid #question
Hybrid side-channel/machine-learning attacks on PUFs: A new threat? (XX, WB), pp. 1–6.
DATE-2014-YamashitaMOT #performance
A smaller and faster variant of RSM (NY, KM, TO, YT), pp. 1–6.
DATE-2014-YangHKKCPK #parallel #predict #simulation
Predictive parallel event-driven HDL simulation with a new powerful prediction strategy (SY, JH, DK, NK, DC, JP, JK), pp. 1–3.
DATE-2014-YangMPOP #logic #using
Complementary resistive switch based stateful logic operations using material implication (YY, JM, DKP, MO, SP), pp. 1–4.
DATE-2014-YasinSE #manycore #polynomial
Unified, ultra compact, quadratic power proxies for multi-core processors (MY, AS, IAME), pp. 1–4.
DATE-2014-YehHN #power management
Leakage-power-aware clock period minimization (HHY, SHH, YTN), pp. 1–6.
DATE-2014-YinOLW #configuration management
Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms (SY, PO, LL, SW), pp. 1–6.
DATE-2014-YuSH #adaptation #scalability
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs (HY, RS, YH), pp. 1–6.
DATE-2014-YuSHEAB #estimation #performance #physics
Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation (LY, SS, CH, IME, DAA, DSB), pp. 1–6.
DATE-2014-ZangenehJ #design #feedback #logic #using
Sub-threshold logic circuit design using feedback equalization (MZ, AJ), pp. 1–6.
DATE-2014-ZebeleinHFST #communication #modelling #multi #protocol
Model-based actor multiplexing with application to complex communication protocols (CZ, CH, JF, TS, JT), pp. 1–4.
DATE-2014-ZhangAJC #manycore #network
Thermal management of manycore systems with silicon-photonic networks (TZ, JLA, AJ, AKC), pp. 1–6.
DATE-2014-ZhangB #analysis #probability
Stochastic analysis of Bubble Razor (GZ, PAB), pp. 1–6.
DATE-2014-ZhangDGLZXS #framework #named #simulation
MSim: A general cycle accurate simulation platform for memcomputing studies (CZ, PD, HG, JL, QZ, JX, YS), pp. 1–5.
DATE-2014-ZhangLHCW #multi #performance #predict
Joint Virtual Probe: Joint exploration of multiple test items’ spatial patterns for efficient silicon characterization and test prediction (SZ, FL, CKH, KTC, HW), pp. 1–6.
DATE-2014-ZhangS #automation #design #specification
Automatic specification granularity tuning for design space exploration (JZ, GS), pp. 1–6.
DATE-2014-ZhangWSX #clustering
Lifetime holes aware register allocation for clustered VLIW processors (XZ, HW, HS, JX), pp. 1–4.
DATE-2014-ZhangYW #analysis #performance #problem
Efficient high-sigma yield analysis for high dimensional problems (MZ, ZY, YW), pp. 1–6.
DATE-2014-ZhangZKKQZRC #power management
Spintronics for low-power computing (YZ, WZ, JOK, WK, DQ, YZ, DR, CC), pp. 1–6.
DATE-2014-ZhaoL #bound
Empowering study of delay bound tightness with simulated annealing (XZ, ZL), pp. 1–6.
DATE-2014-ZhuCYP
Application mapping for express channel-based networks-on-chip (DZ, LC, SY, MP), pp. 1–6.
DATE-2014-ZhuGBS #data flow #graph #scheduling
Memory-constrained static rate-optimal scheduling of synchronous dataflow graphs via retiming (XYZ, MG, TB, SS), pp. 1–6.
DATE-2014-ZhuWCP #design #energy
Optimal design and management of a smart residential PV and energy storage system (DZ, YW, NC, MP), pp. 1–6.
DATE-2014-ZschieschangRKTZLBRBXMK #flexibility
Low-voltage organic transistors for flexible electronics (UZ, RR, UK, KT, TZ, FL, JB, HR, JNB, WX, BM, HK), pp. 1–6.
DATE-2014-ZuoloZMGICPOB #design #fine-grained #framework #named
SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives (LZ, CZ, RM, SG, MI, SDC, PP, PO, DB), pp. 1–6.
DATE-2014-ZussaDTDMGCT #detection #fault #injection #performance
Efficiency of a glitch detector against electromagnetic fault injection (LZ, AD, KT, JMD, PM, LGS, JC, AT), pp. 1–6.
DATE-2014-ZygmontowiczDCP #network
Making it harder to unlock an LSIB: Honeytraps and misdirection in a P1687 network (AZ, JD, AC, JCP), pp. 1–6.

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