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Travelled to:
1 × Germany
Collaborated with:
R.Castro-López E.Roca F.V.Fernández
Talks about:
implement (1) hierarch (1) composit (1) perform (1) circuit (1) analog (1) model (1) issu (1)

Person: M. Velasco-Jimenez

DBLP DBLP: Velasco-Jimenez:M=

Contributed to:

DATE 20142014

Wrote 1 papers:

DATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance
Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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