Travelled to:1 × Germany
1 × United Kingdom
2 × France
2 × USA
Collaborated with:M.A.Peña J.Cortadella M.Solé A.B.Smirnov O.Roig S.Lorite A.Muñoz J.Tornero P.Ponsa A.L.Semenov A.Yakovlev
Talks about:circuit (3) verif (3) asynchron (2) concurr (2) system (2) supervisori (1) synthesi (1) synchron (1) interfac (1) independ (1)
Person: Enric Pastor
DBLP: Pastor:Enric
Contributed to:
2013
2005
200320021998
1997Wrote 7 papers:
- HCI-AMTE-2013-LoriteMTPP #design #interface
- Supervisory Control Interface Design for Unmanned Aerial Vehicles through GEDIS-UAV (SL, AM, JT, PP, EP), pp. 231–240.
- CAV-2005-PastorPS #concurrent #named #verification
- TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems (EP, MAP, MS), pp. 424–428.
- DATE-2003-PastorP #concurrent #simulation #traversal #verification
- Combining Simulation and Guided Traversal for the Verification of Concurrent Systems (EP, MAP), pp. 11158–11159.
- DATE-2002-PenaCSP #case study #verification
- A Case Study for the Verification of Complex Timed Circuits: IPCMOS (MAP, JC, ABS, EP), pp. 44–51.
- DATE-1998-PastorC #analysis #encoding #performance #petri net
- Efficient Encoding Schemes for Symbolic Analysis of Petri Nets (EP, JC), pp. 790–795.
- DAC-1997-RoigCPP #automation #generative
- Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits (OR, JC, MAP, EP), pp. 620–625.
- DAC-1997-SemenovYPPC #independence #synthesis
- Synthesis of Speed-Independent Circuits from STG-Unfolding Segment (ALS, AY, EP, MAP, JC), pp. 16–21.