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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
G.G.E.Gielen J.Vandenbussche K.Uyttenhove M.Steyaert
Talks about:
convert (3) systemat (2) interpol (2) design (2) bit (2) averag (1) speed (1) power (1) model (1) estim (1)

Person: Erik Lauwers

DBLP DBLP: Lauwers:Erik

Contributed to:

DAC 20022002
DATE 20022002
DATE 19991999

Wrote 3 papers:

DAC-2002-VandenbusscheULSG #design
Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter (JV, KU, EL, MS, GGEG), pp. 449–454.
DATE-2002-VandenbusscheLUSG #design
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter (JV, EL, KU, MS, GGEG), pp. 357–361.
DATE-1999-LauwersG #estimation #performance
A Power Estimation Model for High-Speed CMOS A/D Converters (EL, GGEG), pp. 401–405.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.