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Travelled to:
1 × USA
Collaborated with:
S.Bobba I.N.Hajj
Talks about:
circuit (1) analysi (1) suppli (1) static (1) propag (1) includ (1) effect (1) power (1) delay (1) vlsi (1)

Person: Geng Bai

DBLP DBLP: Bai:Geng

Contributed to:

DAC 20012001

Wrote 1 papers:

DAC-2001-BaiBH #analysis #power management
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.