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Travelled to:
2 × France
7 × USA
Collaborated with:
F.N.Najm H.Kriplani G.I.Stamoulis M.R.Becer D.Blaauw R.Panda V.Zolotov G.Bai S.Bobba S.Ramprasad N.R.Shanbhag V.Saxena S.Goel P.Chung Y.Wang D.G.Saab A.T.Yang P.Yang I.Algor C.Oh
Talks about:
circuit (7) estim (5) nois (4) signal (3) power (3) crosstalk (2) techniqu (2) sequenti (2) maximum (2) current (2)

Person: Ibrahim N. Hajj

DBLP DBLP: Hajj:Ibrahim_N=

Contributed to:

DAC 20032003
DATE 20022002
DAC 20012001
DAC 19971997
ED&TC 19971997
DAC 19951995
DAC 19931993
DAC 19921992
DAC 19881988

Wrote 11 papers:

DAC-2003-BecerBAPOZH #reduction
Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
DATE-2002-BecerZBPH #analysis #using
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DAC-2001-BaiBH #analysis #power management
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
DAC-1997-RamprasadSH #estimation #process #statistics
Analytical Estimation of Transition Activity From Word-Level Signal Statistics (SR, NRS, INH), pp. 582–587.
EDTC-1997-SaxenaNH #approach #estimation #monte carlo
Monte-Carlo approach for power estimation in sequential circuits (VS, FNN, INH), pp. 416–420.
DAC-1995-NajmGH #estimation
Power Estimation in Sequential Circuits (FNN, SG, INH), pp. 635–640.
DAC-1993-ChungWH #design #fault #logic
Diagnosis and Correction of Logic Design Errors in Digital Circuits (PYC, YMW, INH), pp. 503–508.
DAC-1993-KriplaniNYH #correlation
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits (HK, FNN, PY, INH), pp. 384–388.
DAC-1993-StamoulisH #correlation #probability #simulation
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects (GIS, INH), pp. 379–383.
DAC-1992-KriplaniNH #estimation
Maximum Current Estimation in CMOS Circuits (HK, FNN, INH), pp. 2–7.
DAC-1988-SaabYH #modelling
Delay Modeling and Time of Bipolar Digital Circuits (DGS, ATY, INH), pp. 288–293.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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