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Travelled to:
1 × USA
Collaborated with:
A.C.Wu Y.Lin
Talks about:
resynthesi (1) floorplan (1) interact (1) method (1) driven (1) macro (1) time (1) soft (1) chip (1)

Person: Hsiao-Pin Su

DBLP DBLP: Su:Hsiao=Pin

Contributed to:

DAC 19991999

Wrote 1 papers:

DAC-1999-SuWL #interactive
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (HPS, ACHW, YLL), pp. 262–267.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.