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Travelled to:
1 × Germany
2 × France
4 × USA
Collaborated with:
W.Fang W.Kuo T.Hwang Y.Lin Y.Lee H.Su T.Yen A.C.Chang J.Y.Lo T.Wu T.Tien
Talks about:
method (4) perform (3) driven (3) design (3) partit (2) custom (2) applic (2) multi (2) time (2) fpga (2)

Person: Allen C.-H. Wu

DBLP DBLP: Wu:Allen_C==H=

Contributed to:

DATE v1 20042004
DATE 20032003
DAC 19991999
DAC 19981998
DAC 19971997
DAC 19951995

Wrote 9 papers:

DATE-v1-2004-KuoHW #composition #design #power management
Decomposition of Instruction Decoder for Low Power Design (WAK, TH, ACHW), pp. 664–665.
DATE-2003-ChangKWH #named
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer (ACYC, WAK, ACHW, TH), pp. 11134–11135.
DATE-2003-LoKWH #design #identification #standard
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs (JYLL, WAK, ACHW, TH), pp. 11102–11103.
DAC-1999-SuWL #interactive
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (HPS, ACHW, YLL), pp. 262–267.
DAC-1998-FangW #clustering #functional #multi #replication #using
Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication (WJF, ACHW), pp. 283–286.
DAC-1997-FangW #clustering #design #multi
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy (WJF, ACHW), pp. 518–521.
DAC-1997-FangWY #debugging #online #realtime
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications (WJF, ACHW, TYY), pp. 101–106.
DAC-1995-LeeW #performance
A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.
EDAC-1994-WuTWL #behaviour #synthesis
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior (TYW, TCT, ACHW, YLL), pp. 277–281.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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