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Travelled to:
6 × USA
Collaborated with:
A.M.Despain F.Yang C.Kao T.Lu Y.Lin W.Shiue C.Lin W.Huang C.Lai I.Pyo C.Su K.Pan Y.Koh C.Tsui H.Chen G.Cheng S.Liu S.Wu
Talks about:
microprocessor (4) trace (4) instruct (3) design (3) synthesi (2) compress (2) resolut (2) pipelin (2) multi (2) embed (2)

Person: Ing-Jer Huang

DBLP DBLP: Huang:Ing=Jer

Contributed to:

DAC 20092009
DAC 20082008
DAC 20072007
DAC 19991999
DAC 19941994
DAC 19921992

Wrote 8 papers:

DAC-2009-LaiYKH #performance #realtime
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC (CHL, FCY, CFK, IJH), pp. 136–141.
DAC-2008-LinSH #multi #realtime
A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer (YTL, WCS, IJH), pp. 862–865.
DAC-2007-KaoHL #embedded #integration #multi
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration (CFK, IJH, CHL), pp. 477–482.
DAC-2007-YangHH #automation #behaviour #design #verification
Automatic Verification of External Interrupt Behaviors for Microprocessor Design (FCY, WKH, IJH), pp. 896–901.
DAC-1999-HuangL #embedded #named
ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers (IJH, TAL), pp. 580–585.
DAC-1994-HuangD #pipes and filters #set #synthesis
Synthesis of Instruction Sets for Pipelined Microprocessors (IJH, AMD), pp. 5–11.
DAC-1992-HuangD #compilation #pipes and filters #set #synthesis
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers (IJH, AMD), pp. 135–140.
DAC-1992-PyoSHPKTCCLWD #automation #design
Application-Driven Design Automation for Microprocessor Design (IP, CLS, IJH, KRP, YSK, CYT, HTC, GC, SL, SW, AMD), pp. 512–517.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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