Travelled to:1 × France
1 × Germany
Collaborated with:C.Chang C.H.Wen J.Zeng M.S.Abadir J.A.Abraham
Talks about:microprocessor (1) diagnosi (1) process (1) identif (1) variat (1) design (1) applic (1) scale (1) power (1) first (1)
Person: Jayanta Bhadra
DBLP: Bhadra:Jayanta
Contributed to:
20132001Wrote 2 papers:
- DATE-2013-ChangWB #design
- Process-variation-aware Iddq diagnosis for nano-scale CMOS designs — the first step (CLC, CHPW, JB), pp. 454–457.
- DATE-2001-ZengABA #identification
- Full chip false timing path identification: applications to the PowerPCTM microprocessors (JZ, MSA, JB, JAA), pp. 514–519.