BibSLEIGH — Proceedings of the 17th Conference on Design, Automation and Test in Europe

Enrico Macii
Proceedings of the 17th Conference on Design, Automation and Test in Europe
DATE, 2013.

SYS

@proceedings{DATE-2013,
	acmid         = "2485288",
	address       = "Grenoble, France",
	editor        = "Enrico Macii",
	isbn          = "978-1-4503-2153-2",
	publisher     = "{EDA Consortium San Jose, CA, USA / ACM DL}",
	title         = "{Proceedings of the 17th Conference on Design, Automation and Test in Europe}",
	year          = 2013,
}

Contents (359 items)

DATE-2013-Vigna #internet: Smart systems for internet of things (BV), p. 1.
DATE-2013-Pedram #communication #framework: Creating a sustainable information and communication infrastructure (MP), p. 2.
DATE-2013-ChenD #parallel #predict #simulation #using: Optimized out-of-order parallel discrete event simulation using predictions (WC, RD), pp. 3–8.
DATE-2013-Moy #approach #modelling #parallel #programming: Parallel programming with SystemC for loosely timed models: a non-intrusive approach (MM), pp. 9–14.
DATE-2013-NovoAI #estimation #fault #fixpoint #invariant #linear #trade-off: Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems (DN, SEA, PI), pp. 15–20.
DATE-2013-AhmadyanKV #algorithm #incremental #runtime #using #verification: Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm (SNA, JAK, SV), pp. 21–26.
DATE-2013-NiakiS #automation #embedded #parallel #simulation: An automated parallel simulation flow for heterogeneous embedded systems (SHAN, IS), pp. 27–30.
DATE-2013-LishernessLC #analysis #mutation testing: Mutation analysis with coverage discounting (PL, NL, KT(C), pp. 31–34.
DATE-2013-LeGD #design #fault #locality #scalability: Scalable fault localization for SystemC TLM designs (HML, DG, RD), pp. 35–38.
DATE-2013-RaghunathanTGM #multi #named #process: Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.
DATE-2013-ChenHBK #energy #multi #optimisation #pipes and filters #worst-case: Energy optimization with worst-case deadline guarantee for pipelined multiprocessor systems (GC, KH, CB, AK), pp. 45–50.
DATE-2013-ShafiqueVH #adaptation #hybrid #manycore #power management #self: Self-adaptive hybrid dynamic power management for many-core systems (MS, BV, JH), pp. 51–56.
DATE-2013-LiYHL #adaptation #named #smarttech #user interface: SmartCap: user experience-oriented power adaptation for smartphone’s application processor (XL, GY, YH, XL), pp. 57–60.
DATE-2013-KimJC #estimation #mobile #runtime: Runtime power estimation of mobile AMOLED displays (DK, WJ, HC), pp. 61–64.
DATE-2013-HongK #architecture #named: AVICA: an access-time variation insensitive L1 cache architecture (SH, SK), pp. 65–70.
DATE-2013-ChenL #2d #architecture #data access #memory management: Dual-addressing memory architecture for two-dimensional memory access patterns (YHC, YYL), pp. 71–76.
DATE-2013-HameedBH #adaptation #multi: Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores (FH, LB, JH), pp. 77–82.
DATE-2013-LorenteVSPCLD #power management #ram: Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes (VL, AV, JS, SP, RC, PL, JD), pp. 83–88.
DATE-2013-El-NacouziAPZJM #detection #scalability: A dual grain hit-miss detector for large die-stacked DRAM caches (MEN, IA, MP, JZ, NDEJ, AM), pp. 89–92.
DATE-2013-Rodriguez-RodriguezCCPT #memory management #performance #policy #using: Reducing writes in phase-change memory environments by using efficient cache replacement policies (RRR, FC, DC, LP, FT), pp. 93–96.
DATE-2013-RustLP #architecture #complexity #using: Low complexity QR-decomposition architecture using the logarithmic number system (JR, FL, SP), pp. 97–102.
DATE-2013-YuehCM #architecture #quality: Perceptual quality preserving SRAM architecture for color motion pictures (WY, MC, SM), pp. 103–108.
DATE-2013-MurugappaBJ #multi #standard: Parameterized area-efficient multi-standard turbo decoder (PM, AB, MJ), pp. 109–114.
DATE-2013-KhanBBSH #video: An H.264 Quad-FullHD low-latency intra video encoder (MUKK, JMB, LB, MS, JH), pp. 115–120.
DATE-2013-ZhuTSHSS #communication: A 100 GOPS ASP based baseband processor for wireless communication (ZZ, ST, YS, JH, GS, JS), pp. 121–124.
DATE-2013-KhanSGH #collaboration #complexity #reduction: Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder (MUKK, MS, MG, JH), pp. 125–128.
DATE-2013-HamdiouiNGGGB #challenge #realtime #reliability: Reliability challenges of real-time systems in forthcoming technology nodes (SH, MN, DG, AG, GG, PB), pp. 129–134.
DATE-2013-NeukirchnerQMAE #analysis #realtime: Sensitivity analysis for arbitrary activation patterns in real-time systems (MN, SQ, TM, PA, RE), pp. 135–140.
DATE-2013-ZhaoGZ #named #scheduling: PT-AMC: integrating preemption thresholds into mixed-criticality scheduling (QZ, ZG, HZ), pp. 141–146.
DATE-2013-SuZ #algorithm #scheduling: An elastic mixed-criticality task model and its scheduling algorithm (HS, DZ), pp. 147–152.
DATE-2013-CarvajalF #framework #platform #realtime: An open platform for mixed-criticality real-time ethernet (GC, SF), pp. 153–156.
DATE-2013-WolfD #composition #integration: Modular SoC integration with subsystems: the audio subsystem case (PvdW, RD), pp. 157–162.
DATE-2013-ThomasMHMK: Configurability in IP subystems: baseband examples (PXT, GM, DH, DM, JK), pp. 163–168.
DATE-2013-MartinB #configuration management #integration: Configurable I/O integration to reduce system-on-chip time to market: DDR, PCIe examples (FM, PB), p. 169.
DATE-2013-LindwerP #integration #mobile: High-performance imaging subsystems and their integration in mobile devices (ML, MRP), p. 170.
DATE-2013-ZhaoOX #process #synthesis: Profit maximization through process variation aware high level synthesis with speed binning (MZ, AO, CJX), pp. 176–181.
DATE-2013-Hara-AzumiFKT #process: Instruction-set extension under process variation and aging effects (YHA, FF, SK, MBT), pp. 182–187.
DATE-2013-BarrioHMMM #multi #synthesis: Multispeculative additive trees in high-level synthesis (AADB, RH, SOM, JMM, MCM), pp. 188–193.
DATE-2013-CanisAB #multi #reduction #synthesis: Multi-pumping for resource reduction in FPGA high-level synthesis (AC, JHA, SDB), pp. 194–197.
DATE-2013-ChenZ #design #optimisation: Resource-constrained high-level datapath optimization in ASIP design (YC, HZ), pp. 198–201.
DATE-2013-YetimMM #streaming: Extracting useful computation from error-prone processors for streaming applications (YY, MM, SM), pp. 202–207.
DATE-2013-HuYH0 #concurrent #low cost #multi #named #thread: Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications (XH, GY, YH, XL), pp. 208–213.
DATE-2013-NikolaouSNOI #array #memory management #question: Memory array protection: check on read or check on write? (PN, YS, LN, EÖ, SI), pp. 214–219.
DATE-2013-YalcinUC #detection #fault #hardware #memory management #named #transaction #using: FaulTM: error detection and recovery using hardware transactional memory (GY, OSÜ, AC), pp. 220–225.
DATE-2013-JimenezNI #named: Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime (XJ, DN, PI), pp. 226–229.
DATE-2013-DiversiBTBB #identification: SCC thermal model identification via advanced bias-compensated least-squares (RD, AB, AT, FB, LB), pp. 230–235.
DATE-2013-0001WAWG #3d #energy #modelling: System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs (KC, CW, BA, NW, KG), pp. 236–241.
DATE-2013-LeeVTS #design #energy #performance: Design of low energy, high performance synchronous and asynchronous 64-point FFT (WL, VSV, ART, KSS), pp. 242–247.
DATE-2013-SchryverTW #monte carlo #multi: A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model (CdS, PT, NW), pp. 248–253.
DATE-2013-ParkCA #energy: Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor (JP, AC, JAA), pp. 254–257.
DATE-2013-ShenQ #energy #performance #smarttech #streaming #video: User-aware energy efficient streaming strategy for smartphone based video playback applications (HS, QQ), pp. 258–261.
DATE-2013-AdnanG #in the cloud: Utility-aware deferred load balancing in the cloud driven by dynamic pricing of electricity (MAA, RG), pp. 262–265.
DATE-2013-ZapaterAMVGC #energy #performance: Leakage and temperature aware server control for improving energy efficiency in data centers (MZ, JLA, JMM, KV, KCG, AKC), pp. 266–269.
DATE-2013-OborilT #design #pipes and filters: MTTF-balanced pipeline design (FO, MBT), pp. 270–275.
DATE-2013-WagnerW #analysis #performance #statistics: Efficient variation-aware statistical dynamic timing analysis for delay test applications (MW, HJW), pp. 276–281.
DATE-2013-LaiCAG #monitoring #named #online: SlackProbe: a low overhead in situ on-line timing slack monitoring methodology (LL, VC, RCA, PG), pp. 282–287.
DATE-2013-ZhangYH0 #testing: Capturing post-silicon variation by layout-aware path-delay testing (XZ, JY, YH, XL), pp. 288–291.
DATE-2013-SureshYOS #adaptation #multi #reduction: Adaptive reduction of the frequency search space for multi-vdd digital circuits (CKHS, EY, SO, OS), pp. 292–295.
DATE-2013-GuanYL0 #analysis #approach #estimation: FIFO cache analysis for WCET estimation: a quantitative approach (NG, XY, ML, WY), pp. 296–301.
DATE-2013-NegreanKE #analysis #manycore: Timing analysis of multi-mode applications on AUTOSAR conform multi-core systems (MN, SK, RE), pp. 302–307.
DATE-2013-ShahKA #analysis #bound: Bounding SDRAM interference: detailed analysis vs. latency-rate analysis (HS, AK, BA), pp. 308–313.
DATE-2013-GhaidaG #design #development #multi #process: Role of design in multiple patterning: technology development, design enablement and process control (RSG, PG), pp. 314–319.
DATE-2013-LinHLFGHM #challenge #detection #fault #validation: Overcoming post-silicon validation challenges through quick error detection (QED) (DL, TH, YL, FF, DSG, NH, SM), pp. 320–325.
DATE-2013-GielenM #modelling #probability #simulation: Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS (GGEG, EM), pp. 326–331.
DATE-2013-GhiribaldiBN #architecture #effectiveness #manycore: A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems (AG, DB, SMN), pp. 332–337.
DATE-2013-ChenPKSCP #configuration management #named: SMART: a single-cycle reconfigurable NoC for SoC applications (CHOC, SP, TK, SS, APC, LSP), pp. 338–343.
DATE-2013-DimitrakopoulosGNK #multi: Switch folding: network-on-chip routers with time-multiplexed output ports (GD, NG, CN, EK), pp. 344–349.
DATE-2013-AkhlaghiKAP #architecture #network #performance: An efficient network on-chip architecture based on isolating local and non-local communications (VA, MK, AAK, MP), pp. 350–353.
DATE-2013-QianJBTMM #analysis #named #performance #using: SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model (ZQ, DCJ, PB, CYT, DM, RM), pp. 354–357.
DATE-2013-AitkenFKRR #analysis #how #question #reliability: Reliability analysis reloaded: how will we survive? (RA, GF, ZTK, FR, MSR), pp. 358–367.
DATE-2013-BoettcherGAK #energy #multi #named: MALEC: a multiple access low energy cache (MB, GG, BMAH, DK), pp. 368–373.
DATE-2013-WangW #named #performance #ram: TreeFTL: efficient RAM management for high performance of NAND flash-based storage systems (CW, WFW), pp. 374–379.
DATE-2013-GuoWLLLC #named: DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems (JG, WW, YZ, SL, HL, YC), pp. 380–385.
DATE-2013-YueZ #memory management #performance: Exploiting subarrays inside a bank to improve phase change memory performance (JY, YZ), pp. 386–391.
DATE-2013-NugterenBC #architecture #future of #parametricity: Future of GPGPU micro-architectural parameters (CN, GJvdB, HC), pp. 392–395.
DATE-2013-DoganBCABA #analysis #embedded #execution #multi #platform #power management: Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms (AYD, RB, JC, GA, AB, DA), pp. 396–399.
DATE-2013-JooyaB #power management #using: Using synchronization stalls in power-aware accelerators (AJ, AB), pp. 400–403.
DATE-2013-TheissingMSSS #analysis #fault: Comprehensive analysis of software countermeasures against fault attacks (NT, DM, MS, FS, GS), pp. 404–409.
DATE-2013-BayrakVRNBI: An EDA-friendly protection scheme against side-channel attacks (AGB, NV, FR, DN, PB, PI), pp. 410–415.
DATE-2013-YinQZ #design #implementation: Design and implementation of a group-based RO PUF (CEDY, GQ, QZ), pp. 416–421.
DATE-2013-YaoKLMK #named #network #physics: ClockPUF: physical unclonable functions based on clock networks (YY, MK, JL, ILM, FK), pp. 422–427.
DATE-2013-KoeberlKS #generative: Memristor PUFs: a new generation of memory-based physically unclonable functions (PK, ÜK, ARS), pp. 428–431.
DATE-2013-DiazSSR #analysis #network #performance #security #simulation: Wireless sensor network simulation for security and performance analysis (AD, PS, JS, JR), pp. 432–435.
DATE-2013-HillebrechtKEWB #generative: Accurate QBF-based test pattern generation in presence of unknown values (SH, MAK, DE, HJW, BB), pp. 436–441.
DATE-2013-ZordanBDGTVB #fault #power management: Test solution for data retention faults in low-power SRAMs (LBZ, AB, LD, PG, AT, AV, NB), pp. 442–447.
DATE-2013-SauerRSPB #performance #satisfiability: Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths (MS, SR, TS, IP, BB), pp. 448–453.
DATE-2013-ChangWB #design: Process-variation-aware Iddq diagnosis for nano-scale CMOS designs — the first step (CLC, CHPW, JB), pp. 454–457.
DATE-2013-SagstetterLSWBHJPPC #architecture #challenge #design #hardware #security: Security challenges in automotive hardware/software architecture design (FS, ML, SS, MW, AB, WRH, SJ, TP, AP, SC), pp. 458–463.
DATE-2013-RajovicRVGPR #case study #energy #experience #mobile #performance: Experiences with mobile processors for energy efficient HPC (NR, AR, JV, IG, NP, AR), pp. 464–468.
DATE-2013-Vigouroux #design #question #what: What designs for coming supercomputers? (XV), p. 469.
DATE-2013-Lehner #database #energy #in memory: Energy-efficient in-memory database computing (WL), pp. 470–474.
DATE-2013-StanisicVCDMLM #analysis #embedded #performance #platform #power management: Performance analysis of HPC applications on low-power embedded platforms (LS, BV, JC, AD, VMM, AL, JFM), pp. 475–480.
DATE-2013-KappelHHHHH #concept #energy #power management #self: Alternative power supply concepts for self-sufficient wireless sensor nodes by energy harvesting (RK, GH, GH, TH, GH, GH), p. 481.
DATE-2013-Mitcheson #adaptation #delivery #energy #performance #question: Adaptable, high performance energy harvesters: can energy harvesting deliver enough power for automotive electronics? (PDM), p. 482.
DATE-2013-GrimmMP #challenge #power management: Ultra-low power: an EDA challenge (CG, JM, XP), p. 483.
DATE-2013-KazmierskiWAM #energy #optimisation #performance: DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters (TJK, LW, BMAH, GVM), p. 484.
DATE-2013-LiD #approach #debugging #hybrid #performance: A hybrid approach for fast and accurate trace signal selection for post-silicon debug (ML, AD), pp. 485–490.
DATE-2013-DeOrioLBB #debugging #detection #machine learning: Machine learning-based anomaly detection for post-silicon bug diagnosis (AD, QL, MB, VB), pp. 491–496.
DATE-2013-ChandranSP #validation: Space sensitive cache dumping for post-silicon validation (SC, SRS, PRP), pp. 497–502.
DATE-2013-CevreroEAILBS #estimation #performance: Fast and accurate BER estimation methodology for I/O links based on extreme value theory (AC, NEE, CA, PI, YL, AB, GIS), pp. 503–508.
DATE-2013-JainTG #automation: Automated determination of top level control signals (RKJ, PT, SG), pp. 509–512.
DATE-2013-KosmidisAQC #design #realtime: A cache design for probabilistically analysable real-time systems (LK, JA, EQ, FJC), pp. 513–518.
DATE-2013-KinsyCKD #architecture #grid #named #smarttech: MARTHA: architecture for control and emulation of power electronics and smart grid systems (MAK, IC, OK, SD), pp. 519–524.
DATE-2013-GoossensAG #memory management #policy: Conservative open-page policy for mixed time-criticality memory controllers (SG, BA, KG), pp. 525–530.
DATE-2013-ThabetLAPD #architecture #flexibility #hardware #manycore #performance: An efficient and flexible hardware support for accelerating synchronization operations on the STHORM many-core architecture (FT, YL, CA, JMP, RD), pp. 531–534.
DATE-2013-RakossyHTSNO #architecture #array #fault #functional #testing: Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array (ZER, MH, HT, TS, YN, HO), pp. 535–540.
DATE-2013-RahimiMBGB #clustering: Variation-tolerant OpenMP tasking on tightly-coupled processor clusters (AR, AM, PB, RKG, LB), pp. 541–546.
DATE-2013-WangSCC #design #embedded #estimation #performance #reliability: Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design (ZW, KS, CC, AC), pp. 547–552.
DATE-2013-HuangKCM #correlation #modelling #testing: Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests (KH, NK, JMCJ, YM), pp. 553–558.
DATE-2013-HuHMCF #detection #fault #realtime: Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips (KH, BNH, AM, KC, RBF), pp. 559–564.
DATE-2013-YilmazSWO #analysis #fault #industrial #scalability #simulation: Fault analysis and simulation of large scale industrial mixed-signal circuits (EY, GS, LW, SO), pp. 565–570.
DATE-2013-DengKNOYOBKPD: Electrical calibration of spring-mass MEMS capacitive accelerometers (LD, VK, NSJN, MKO, EY, SO, BB, SK, DP, TD), pp. 571–574.
DATE-2013-AliasDP #kernel #optimisation #synthesis: Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA (CA, AD, AP), pp. 575–580.
DATE-2013-HanxledenMADFMMO #concurrent: Sequentially constructive concurrency: a conservative extension of the synchronous model of computation (RvH, MM, JA, BD, IF, CM, SM, OO), pp. 581–586.
DATE-2013-WangH #embedded #modelling #performance #simulation: Fast and accurate cache modeling in source-level simulation of embedded software (ZW, JH), pp. 587–592.
DATE-2013-BaiS #architecture #automation #data transformation #manycore #memory management #performance: Automatic and efficient heap data management for limited local memory multicore architectures (KB, AS), pp. 593–598.
DATE-2013-HuZXTS #embedded #hybrid #in memory #memory management: Software enabled wear-leveling for hybrid PCM main memory on embedded systems (JH, QZ, CJX, WCT, EHMS), pp. 599–602.
DATE-2013-KosmidisCQABC #analysis #design #probability: Probabilistic timing analysis on conventional cache designs (LK, CC, EQ, JA, EDB, FJC), pp. 603–606.
DATE-2013-AyadAMSL #energy #integration #variability: HW-SW integration for energy-efficient/variability-aware computing (GA, AA, EM, BS, RL), pp. 607–611.
DATE-2013-De #design: Near-threshold voltage design in nanoscale CMOS (VD), p. 612.
DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design: Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
DATE-2013-WeiSHCLLZWM #challenge: Carbon nanotube circuits: opportunities and challenges (HW, MMS, GH, HYC, CSL, LL, JZ, HSPW, SM), pp. 619–624.
DATE-2013-GaillardonABMSLM: Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
DATE-2013-FreitasRS #concurrent #consistency #memory management #on the fly #verification: On-the-fly verification of memory consistency with concurrent relaxed scoreboards (LSF, EAR, LCVdS), pp. 631–636.
DATE-2013-LuMS #embedded #performance #simulation: Fast cache simulation for host-compiled simulation of embedded software (KL, DMG, US), pp. 637–642.
DATE-2013-YuZHWLT #approach #manycore #set #simulation: A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations (FWY, BHZ, YHH, HIW, CRL, RST), pp. 643–648.
DATE-2013-LiZCZ #analysis #multi #simulation: Multi-level phase analysis for sampling simulation (JL, WZ, HC, BZ), pp. 649–654.
DATE-2013-LyrasRPS #multi #scalability #simulation: Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems (GL, DR, AP, DS), pp. 655–658.
DATE-2013-XydisPZS #architecture #compilation #framework #metamodelling #parametricity #synthesis: A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization (SX, GP, VZ, CS), pp. 659–664.
DATE-2013-SampaioZSABH #energy #estimation #memory management #multi #video: Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding (FS, BZ, MS, LVA, SB, JH), pp. 665–670.
DATE-2013-PaoneVZSMHL #embedded #manycore #modelling #platform #simulation: Improving simulation speed and accuracy for many-core embedded platforms with ensemble models (EP, NV, VZ, CS, DM, GH, TL), pp. 671–676.
DATE-2013-RizkBJMA #case study #design: Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization (MR, AB, MJ, YM, YA), pp. 677–680.
DATE-2013-GiraoSW #clustering #policy: Exploring resource mapping policies for dynamic clustering on NoC-based MPSoCs (GG, TS, FRW), pp. 681–684.
DATE-2013-ZakharenkoAM #cpu #gpu #performance #using: Characterizing the performance benefits of fused CPU/GPU systems using FusionSim (VZ, TMA, AM), pp. 685–688.
DATE-2013-DasKV #multi: Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems (AD, AK, BV), pp. 689–694.
DATE-2013-WangJSZ #fault tolerance #framework #scheduling: A work-stealing scheduling framework supporting fault tolerance (YW, WJ, FS, QZ), pp. 695–700.
DATE-2013-ImagawaTOS #analysis #architecture #configuration management #effectiveness: A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis (TI, HT, HO, TS), pp. 701–706.
DATE-2013-LiSRRRAHP #configuration management #named: CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-HellwegeHPP #analysis #metric #reliability: Reliability analysis for integrated circuit amplifiers used in neural measurement systems (NH, NH, DPD, SP), pp. 713–716.
DATE-2013-CassanoCKHPS #configuration management #online #testing: On-line testing of permanent radiation effects in reconfigurable systems (LC, DC, SK, JH, MP, LS), pp. 717–720.
DATE-2013-ShreejithVFL #approach #configuration management #network #using: An approach for redundancy in FlexRay networks using FPGA partial reconfiguration (SS, KV, SAF, ML), pp. 721–724.
DATE-2013-WettinMPSG #approach #design #energy #manycore: Energy-efficient multicore chip design through cross-layer approach (PW, JM, PPP, BS, AG), pp. 725–730.
DATE-2013-AmpaduZS #energy #fault tolerance #manycore: Breaking the energy barrier in fault-tolerant caches for multicore systems (PA, MZ, VS), pp. 731–736.
DATE-2013-KavousianosC #testing: Testing for SoCs with advanced static and dynamic power-management capabilities (XK, KC), pp. 737–742.
DATE-2013-MittalBKDKP #adaptation #manycore #towards: Towards adaptive test of multi-core RF SoCs (RM, LB, YBCK, VRD, MK, RAP), pp. 743–748.
DATE-2013-KumarCT #approach #distributed #realtime #satisfiability: A satisfiability approach to speed assignment for distributed real-time systems (PK, DBC, LT), pp. 749–754.
DATE-2013-LagraaTP #concurrent #data access #data mining #identification #memory management #mining #simulation: Data mining MPSoC simulation traces to identify concurrent memory access patterns (SL, AT, FP), pp. 755–760.
DATE-2013-KatoenNWSS #energy #modelling #optimisation: Model-based energy optimization of automotive control systems (JPK, TN, HW, TS, DS), pp. 761–766.
DATE-2013-QuintonNE #analysis #formal method #realtime: Formal analysis of sporadic bursts in real-time systems (SQ, MN, RE), pp. 767–772.
DATE-2013-MiyamoriXKUST #development #manycore #power management: Development of low power many-core SoC for multimedia applications (TM, HX, TK, HU, TS, JT), pp. 773–777.
DATE-2013-DarbelL #power management: SoC low-power practices for wireless applications (ND, SL), p. 778.
DATE-2013-DutoitGP #3d #integration #power management: 3D integration for power-efficient computing (DD, EG, IMP), pp. 779–784.
DATE-2013-AbdullaDRSZ #hybrid #liveness #memory management #safety #transaction #verification: Verifying safety and liveness for the FlexTM hybrid transactional memory (PAA, SD, AR, AS, YZ), pp. 785–790.
DATE-2013-WelpK #model checking #reachability: QF BV model checking with property directed reachability (TW, AK), pp. 791–796.
DATE-2013-MishchenkoEBCCS: A semi-canonical form for sequential AIGs (AM, NE, RKB, MLC, PC, NS), pp. 797–802.
DATE-2013-LoiaconoPPPQRVB #estimation #multi #performance #problem: Fast cone-of-influence computation and estimation in problems with multiple properties (CL, MP, PP, DP, SQ, SR, DV, JB), pp. 803–806.
DATE-2013-BackesR #reachability #using: Using cubes of non-state variables with property directed reachability (JDB, MDR), pp. 807–810.
DATE-2013-GoultiaevaSB: Bridging the gap between dual propagation and CNF-based QBF solving (AG, MS, AB), pp. 811–814.
DATE-2013-LifaEP #linear #predict: Dynamic configuration prefetching based on piecewise linear prediction (AAL, PE, ZP), pp. 815–820.
DATE-2013-FarisiBCS #automation #implementation #multi: An automatic tool flow for the combined implementation of multi-mode circuits (BAF, KB, JMPC, DS), pp. 821–826.
DATE-2013-BrandonW #using: Support for dynamic issue width in VLIW processors using generic binaries (AB, SW), pp. 827–832.
DATE-2013-NavasSO #array #configuration management #flexibility #framework #platform #reuse: The RecoBlock SoC platform: a flexible array of reusable run-time-reconfigurable IP-blocks (BN, IS, JÖ), pp. 833–838.
DATE-2013-HsiehWH #configuration management #distributed #named #network: DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks (CMH, ZW, JH), pp. 839–842.
DATE-2013-Pham-QuocHWABB #design #hardware #hybrid: Hybrid interconnect design for heterogeneous hardware accelerators (CPQ, JH, SW, ZAA, JB, KB), pp. 843–846.
DATE-2013-WangDX #named #policy: OAP: an obstruction-aware cache management policy for STT-RAM last-level caches (JW, XD, YX), pp. 847–852.
DATE-2013-BiWL #design: STT-RAM designs supporting dual-port accesses (XB, MAW, HL), pp. 853–858.
DATE-2013-GuoYZC #hybrid #low cost: Low cost power failure protection for MLC NAND flash storage systems with PRAM/DRAM hybrid buffer (JG, JY, YZ, YC), pp. 859–864.
DATE-2013-ShengWLY #named #parallel: SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors (XS, YW, YL, HY), pp. 865–868.
DATE-2013-ZhouZY #design #energy #memory management #network #using: The design of sustainable wireless sensor network node using solar energy and phase change memory (PZ, YZ, JY), pp. 869–872.
DATE-2013-LiBMLO: Optical look up table (ZL, SLB, CM, XL, IO), pp. 873–876.
DATE-2013-MiryalaMCMP #configuration management #logic: A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
DATE-2013-WangLPPC #energy #hybrid: Optimal control of a grid-connected hybrid electrical energy storage system for homes (YW, XL, MP, SP, NC), pp. 881–886.
DATE-2013-LiuN #multi: Radar signature in multiple target tracking system for driver assistant application (HL, SN), pp. 887–892.
DATE-2013-PistorHRTSBGMPKSLPP #development: Development of a fully implantable recording system for ECoG signals (JP, JH, DR, ET, TS, DB, VGG, SM, DPD, AKK, MS, WL, KP, SP), pp. 893–898.
DATE-2013-BraojosAA #classification #embedded #random #using: A methodology for embedded classification of heartbeats using random projections (RB, GA, DA), pp. 899–904.
DATE-2013-WeddellMMBAB #energy #multi #overview: A survey of multi-source energy harvesting systems (ASW, MM, GVM, DB, BMAH, LB), pp. 905–908.
DATE-2013-WangLPKC #architecture #configuration management #cost analysis #design #optimisation: Capital cost-aware design and partial shading-aware architecture optimization of a reconfigurable photovoltaic system (YW, XL, MP, JK, NC), pp. 909–912.
DATE-2013-LotfianJ #architecture #hardware #power management #smarttech #using: An ultra-low power hardware accelerator architecture for wearable computers using dynamic time warping (RL, RJ), pp. 913–916.
DATE-2013-MaricAV #architecture #hybrid #performance #reliability #using: Efficient cache architectures for reliable hybrid voltage operation using EDC codes (BM, JA, MV), pp. 917–920.
DATE-2013-MushtaqAB #approach #fault tolerance #manycore #performance #platform: Efficient software-based fault tolerance approach on multicore platforms (HM, ZAA, KB), pp. 921–926.
DATE-2013-GaoGB #fault tolerance #scheduling #using: Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors (YG, SKG, MAB), pp. 927–932.
DATE-2013-AnanthanarayananGP #detection #fault #low cost #set #using: Low cost permanent fault detection using ultra-reduced instruction set co-processors (SA, SG, HDP), pp. 933–938.
DATE-2013-RienerFF #fault tolerance: Improving fault tolerance utilizing hardware-software-co-synthesis (HR, SF, GF), pp. 939–942.
DATE-2013-YanLH #adaptation #fault #self: A dynamic self-adaptive correction method for error resilient application (LY, HL, ZH), pp. 943–946.
DATE-2013-CoppolaFGK #embedded #manycore: From embedded multi-core SoCs to scale-out processors (MC, BF, JG, GK), pp. 947–951.
DATE-2013-MagarshackFC #design #energy #process: UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency (PM, PF, GC), pp. 952–957.
DATE-2013-FettweisHLF: Wireless interconnect for board and chip level (GF, NuH, LL, EF), pp. 958–963.
DATE-2013-Xie #memory management: Future memory and interconnect technologies (YX0), pp. 964–969.
DATE-2013-KimYIBS #manycore #realtime #scheduling: Optimized scheduling of multi-IMA partitions with exclusive region for synchronized real-time multi-core systems (JEK, MKY, SI, RMB, LS), pp. 970–975.
DATE-2013-GangadharanCZ #platform #scheduling: Quality-aware media scheduling on MPSoC platforms (DG, SC, RZ), pp. 976–981.
DATE-2013-LukasiewyczSC #programming #using: Priority assignment for event-triggered systems using mathematical programming (ML, SS, SC), pp. 982–987.
DATE-2013-CilardoGMM #design #performance #scalability: Efficient and scalable OpenMP-based system-level design (AC, LG, AM, NM), pp. 988–991.
DATE-2013-HeLLHY #streaming #synthesis: Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications (XH, SL, YL, XSH, HY), pp. 992–995.
DATE-2013-BernasconiCTV #using: Minimization of P-circuits using Boolean relations (AB, VC, GT, TV), pp. 996–1001.
DATE-2013-RenPRKWEK #performance #synthesis: Intuitive ECO synthesis for high performance circuits (HR, RP, LNR, SK, CW, JE, JK), pp. 1002–1007.
DATE-2013-LuZ #constraints #fault: Retiming for Soft Error Minimization Under Error-Latching Window Constraints (YL, HZ), pp. 1008–1013.
DATE-2013-AmaruGM #canonical #logic #novel #synthesis: Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits (LGA, PEG, GDM), pp. 1014–1017.
DATE-2013-StergiouJ #dataset #optimisation: Optimizing BDDs for time-series dataset manipulation (SS, JJ), pp. 1018–1021.
DATE-2013-FirouziKTN #analysis #runtime: Incorporating the impacts of workload-dependent runtime variations into timing analysis (FF, SK, MBT, SRN), pp. 1022–1025.
DATE-2013-MandalKM: Exploring topologies for source-synchronous ring-based network-on-chip (AM, SPK, RNM), pp. 1026–1031.
DATE-2013-AncajasCR #approach: Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach (DMA, KC, SR), pp. 1032–1037.
DATE-2013-ZoniF: Sensor-wise methodology to face NBTI stress of NoC buffers (DZ, WF), pp. 1038–1043.
DATE-2013-SparsoKS #interface #network: An area-efficient network interface for a TDM-based network-on-chip (JS, EK, MS), pp. 1044–1047.
DATE-2013-DaneshtalabEPT #interface #manycore #named #network: CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems (MD, ME, JP, HT), pp. 1048–1051.
DATE-2013-JaninBCDEGLT #design: Designing tightly-coupled extension units for the STxP70 processor (YJ, VB, HC, TD, CE, OAG, VL, TT), pp. 1052–1053.
DATE-2013-PiriouDRR #architecture #estimation #performance #programmable #reduction: A fast and accurate methodology for power estimation and reduction of programmable architectures (EP, RD, FR, SR), pp. 1054–1055.
DATE-2013-JoshiLBBG #estimation #performance #statistics: A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits (SJ, AL, MB, EB, SG), pp. 1056–1057.
DATE-2013-KodakaTSYKTXSUTMM #manycore #power management #predict: A near-future prediction method for low power consumption on a many-core processor (TK, AT, SS, AY, TK, TT, HX, TS, HU, JT, TM, NM), pp. 1058–1059.
DATE-2013-ChabrolRDJHOZ #kernel #realtime: Time- and angle-triggered real-time kernel (DC, DR, VD, MJ, MAH, PO, GZ), pp. 1060–1062.
DATE-2013-SchneiderP #adaptation #embedded: An extremely compact JPEG encoder for adaptive embedded systems (JS, SP), pp. 1063–1064.
DATE-2013-DeutschC #multi #using: Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels (SD, KC), pp. 1065–1070.
DATE-2013-BakshiH #reduction #smt #using: LFSR seed computation and reduction using SMT-based fault-chaining (DB, MSH), pp. 1071–1076.
DATE-2013-SarrazinENBG #concurrent #design #detection #fault #performance: Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection (SS, SE, LAdBN, YB, VG), pp. 1077–1082.
DATE-2013-Pomeranz #equivalence #fault #graph #on the #set: On candidate fault sets for fault diagnosis and dominance graphs of equivalence classes (IP), pp. 1083–1088.
DATE-2013-HuangMSBP #effectiveness #performance: A fast and Effective DFT for test and diagnosis of power switches in SoCs (XH, JM, RAS, SB, DKP), pp. 1089–1092.
DATE-2013-AminifarEPC #cyber-physical #design #robust: Control-quality driven design of cyber-physical systems with robustness guarantees (AA, PE, ZP, AC), pp. 1093–1098.
DATE-2013-SchneiderZGMC #analysis #composition: Compositional analysis of switched ethernet topologies (RS, LZ, DG, AM, SC), pp. 1099–1104.
DATE-2013-KloosM #synthesis: Supervisor synthesis for controller upgrades (JK, RM), pp. 1105–1110.
DATE-2013-BundMS #analysis: Event density analysis for event triggered control systems (TB, BM, FS), pp. 1111–1116.
DATE-2013-MuradoreQF #network #predict: Model predictive control over delay-based differentiated services control networks (RM, DQ, PF), pp. 1117–1122.
DATE-2013-GoswamiMSXC #design #multi: Multirate controller design for resource- and schedule-constrained automotive ECUs (DG, AM, RS, CJX, SC), pp. 1123–1126.
DATE-2013-PerelliCMBMB #design #health #monitoring #power management: Design of an ultra-low power device for aircraft structural health monitoring (AP, CC, LDM, DB, AM, LB), pp. 1127–1130.
DATE-2013-Kae-NuneP #anti #process #testing: Qualification and testing process to implement anti-counterfeiting technologies into IC packages (NKN, SP), pp. 1131–1136.
DATE-2013-LeestT #hardware #security: Anti-counterfeiting with hardware intrinsic security (VvdL, PT), pp. 1137–1142.
DATE-2013-Milano #challenge #energy #policy #research: Sustainable energy policies: research challenges and opportunities (MM), pp. 1143–1148.
DATE-2013-GurgenGBG #cyber-physical #self: Self-aware cyber-physical systems and applications in smart buildings and cities (LG, OG, YB, MG), pp. 1149–1154.
DATE-2013-PorcarelliBBP #industrial #low cost #monitoring: Perpetual and low-cost power meter for monitoring residential and industrial appliances (DP, DB, DB, GP), pp. 1155–1160.
DATE-2013-LuMS13a #estimation: Analytical timing estimation for temporally decoupled TLMs considering resource conflicts (KL, DMG, US), pp. 1161–1166.
DATE-2013-FakihGFR #analysis #architecture #model checking #performance #towards #using: Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking (MF, KG, MF, AR), pp. 1167–1172.
DATE-2013-MaYGGTBH #analysis #architecture #towards #validation: Toward polychronous analysis and validation for timed software architectures in AADL (YM, HY, TG, PLG, JPT, LB, MH), pp. 1173–1178.
DATE-2013-MalburgFF #analysis #comprehension #data flow #design: Tuning dynamic data flow analysis to support design understanding (JM, AF, GF), pp. 1179–1184.
DATE-2013-HelmstetterCGMV #performance #simulation #using: Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications (CH, JC, BG, MM, PV), pp. 1185–1188.
DATE-2013-SeiterWSD #ocl #specification #uml #verification: Determining relevant model elements for the verification of UML/OCL specifications (JS, RW, MS, RD), pp. 1189–1192.
DATE-2013-WilleGSKD #modelling #towards #verification: Towards a generic verification methodology for system models (RW, MG, MS, MK, RD), pp. 1193–1196.
DATE-2013-MishraBTRF #energy #power management: A sub-μa power management circuit in 0.18μm CMOS for energy harvesters (BM, CB, GT, CR, PAF), pp. 1197–1202.
DATE-2013-XiaoINSC #power management: Saliency aware display power management (YX, KMI, VN, DS, NC), pp. 1203–1208.
DATE-2013-KahngKP #power management #reduction: Active-mode leakage reduction with data-retained power gating (ABK, SK, BP), pp. 1209–1214.
DATE-2013-WangTSL #algorithm: A power-driven thermal sensor placement algorithm for dynamic thermal management (HW, SXDT, SS, XL), pp. 1215–1220.
DATE-2013-WangXZWYWNW #using: Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.
DATE-2013-XieYPSC #adaptation: Adaptive thermal management for portable system batteries by forced convection cooling (QX, SY, MP, DS, NC), pp. 1225–1228.
DATE-2013-TengT #array #design #reduction: Sparse-rotary oscillator array (SROA) design for power and skew reduction (YT, BT), pp. 1229–1234.
DATE-2013-ShafaeiSP #logic #synthesis: Reversible logic synthesis of k-input, m-output lookup tables (AS, MS, MP), pp. 1235–1240.
DATE-2013-ZhangCBACL #3d #architecture #composition #manycore #named #performance: 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling (TZ, AC, GB, PA, AKC, YL), pp. 1241–1246.
DATE-2013-LiSLXCX #adaptation: Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.
DATE-2013-LefterVTEHC #3d #integration #memory management #question: Is TSV-based 3D integration suitable for inter-die memory repair? (ML, GRV, MT, ME, SH, SDC), pp. 1251–1254.
DATE-2013-ZouZKX #3d #design: Thermomechanical stress-aware management for 3D IC designs (QZ, TZ, EK, YX), pp. 1255–1258.
DATE-2013-RajendranSK #question: Is split manufacturing secure? (JR, OS, RK), pp. 1259–1264.
DATE-2013-ChaG #approach #detection #effectiveness #metric: Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost (BC, SKG), pp. 1265–1270.
DATE-2013-HuNRK #detection #hardware #multimodal #using: High-sensitivity hardware trojan detection using multimodal characterization (KH, ANN, SR, FK), pp. 1271–1276.
DATE-2013-SubramanyanTPRSM #analysis #functional #reverse engineering #using: Reverse engineering digital circuits using functional analysis (PS, NT, KP, DR, AS, SM), pp. 1277–1280.
DATE-2013-ObergMSK #framework #hardware #testing: A practical testing framework for isolating hardware timing channels (JO, SM, TS, RK), pp. 1281–1284.
DATE-2013-CaiHMM #analysis #memory management #modelling: Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling (YC, EFH, OM, KM), pp. 1285–1290.
DATE-2013-YaoYW #adaptation #analysis #modelling #online #performance: Efficient importance sampling for high-sigma yield analysis with adaptive online surrogate modeling (JY, ZY, YW), pp. 1291–1296.
DATE-2013-BeerGCCZ #challenge #metric #simulation: Metastability challenges for 65nm and beyond: simulation and measurements (SB, RG, JC, TC, DMZ), pp. 1297–1302.
DATE-2013-PouyanAMR #adaptation #configuration management #design #implementation: Design and implementation of an adaptive proactive reconfiguration technique for SRAM caches (PP, EA, FM, AR), pp. 1303–1306.
DATE-2013-GomonyAG #architecture #memory management #multi #realtime: Architecture and optimal configuration of a real-time multi-channel memory controller (MDG, BA, KG), pp. 1307–1312.
DATE-2013-YoonKBS #design #multi #optimisation #parametricity #scheduling: Holistic design parameter optimization of multiple periodic resources in hierarchical scheduling (MKY, JEK, RMB, LS), pp. 1313–1318.
DATE-2013-ZhuDNZ #finite #implementation #robust #state machine: Robust and extensible task implementations of synchronous finite state machines (QZ, PD, MDN, HZ), pp. 1319–1324.
DATE-2013-El-ShambakeyR #named #realtime #scheduling: FBLT: a real-time contention manager with improved schedulability (MES, BR), pp. 1325–1330.
DATE-2013-Mueller-GritschnederLWGS #case study #framework #platform #prototype #realtime: A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot (DMG, KL, EW, MG, US), pp. 1331–1334.
DATE-2013-PollexFSMMW #analysis #constant #realtime: Sufficient real-time analysis for an engine control unit with constant angular velocities (VP, TF, FS, UM, RM, GW), pp. 1335–1338.
DATE-2013-RuchBPMM #roadmap #towards: Roadmap towards ultimately-efficient zeta-scale datacenters (PR, TB, SP, GIM, BM), pp. 1339–1344.
DATE-2013-KimRAL #energy #virtual machine: Correlation-aware virtual machine allocation for energy-efficient datacenters (JK, MR, DA, ML), pp. 1345–1350.
DATE-2013-Kozyrakis #performance: Resource efficient computing for warehouse-scale datacenters (CK), pp. 1351–1356.
DATE-2013-BertaccoCBFVKP #on the #using: On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
DATE-2013-VenkataramaniRR #approximate #configuration management #design #named #paradigm #quality: Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits (SV, KR, AR), pp. 1367–1372.
DATE-2013-ChantemYHD #manycore #online #reliability #scheduling: Enhancing multicore reliability through wear compensation in online assignment and scheduling (TC, XY, XSH, RPD), pp. 1373–1378.
DATE-2013-LeeWHY #3d #hybrid #named: NUMANA: a hybrid numerical and analytical thermal simulator for 3-D ICs (YML, THW, PYH, CPY), pp. 1379–1384.
DATE-2013-FourmigueBN #3d #simulation: Explicit transient thermal simulation of liquid-cooled 3D ICs (AF, GB, GN), pp. 1385–1390.
DATE-2013-PaternaR #problem #using: Mitigating dark-silicon problems using superlattice-based thermoelectric coolers (FP, SR), pp. 1391–1394.
DATE-2013-ZhaoLBT #detection #manycore #probability #runtime: Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems (JZ, S(L, WB, RT), pp. 1395–1398.
DATE-2013-MishchenkoEBBMN #abstraction #named #revisited: GLA: gate-level abstraction revisited (AM, NE, RKB, JB, HM, PKN), pp. 1399–1404.
DATE-2013-PigorschS #locality: Lemma localization: a practical method for downsizing SMT-interpolants (FP, CS), pp. 1405–1410.
DATE-2013-Belov0MM #abstraction #satisfiability: Core minimization in SAT-based abstraction (AB, HC, AM, JMS), pp. 1411–1416.
DATE-2013-CabodiLV #bound #model checking #optimisation: Optimization techniques for craig interpolant compaction in unbounded model checking (GC, CL, DV), pp. 1417–1422.
DATE-2013-HasanA #analysis #fault #feedback #formal method #using: Formal analysis of steady state errors in feedback control systems using HOL-light (OH, MA), pp. 1423–1426.
DATE-2013-ElbayoumiHE #concurrent #diagrams #manycore #novel #platform: A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms (ME, MSH, MYE), pp. 1427–1430.
DATE-2013-RethyDSDG #interface #network #power management: A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.
DATE-2013-AhmadyanV #analysis #reachability #reduction #set: Reachability analysis of nonlinear analog circuits through iterative reachable set reduction (SNA, SV), pp. 1436–1441.
DATE-2013-MillerB #parametricity #satisfiability #verification: Formal verification of analog circuit parameters across variation utilizing SAT (MM, FB), pp. 1442–1447.
DATE-2013-JongheDDG #modelling #recursion: Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories (DdJ, DD, TD, GGEG), pp. 1448–1453.
DATE-2013-YuWAEB #modelling #statistics: Statistical modeling with the virtual source MOSFET model (LY, LW, DAA, IME, DSB), pp. 1454–1457.
DATE-2013-ChenWLL #automation #flexibility #process: Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects (YLC, WRW, GRL, CNJL), pp. 1458–1461.
DATE-2013-BernardiBSRB #embedded #fault #identification #online: On-line functionally untestable fault identification in embedded processor cores (PB, MB, ES, MSR, OB), pp. 1462–1467.
DATE-2013-CarreteroHMRV: Capturing vulnerability variations for register files (JC, EH, MM, TR, XV), pp. 1468–1473.
DATE-2013-PontarelliOEW #detection #fault #using: Error detection in ternary CAMs using bloom filters (SP, MO, AE, SJW), pp. 1474–1479.
DATE-2013-ManiatakosMM #array #memory management #optimisation: AVF-driven parity optimization for MBU protection of in-core memory arrays (MM, MKM, YM), pp. 1480–1485.
DATE-2013-ShihW #3d #fault: An enhanced double-TSV scheme for defect tolerance in 3D-IC (HCS, CWW), pp. 1486–1489.
DATE-2013-MohanramWI #certification #compilation #memory management #named #order #reduction: Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification (KM, MW, SI), pp. 1490–1493.
DATE-2013-KocBKE #detection #fault: Exploiting replicated checkpoints for soft error detection and correction (FK, KB, BK, OE), pp. 1494–1497.
DATE-2013-WildermannZT #analysis #distributed #game studies #manycore: Game-theoretic analysis of decentralized core allocation schemes on many-core systems (SW, TZ, JT), pp. 1498–1503.
DATE-2013-BurgioTMB #clustering #fine-grained #memory management: Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters (PB, GT, AM, LB), pp. 1504–1509.
DATE-2013-OjailDLG #embedded #framework #lightweight #manycore #named: ARTM: a lightweight fork-join framework for many-core embedded systems (MO, RD, YL, AG), pp. 1510–1515.
DATE-2013-JahnH #architecture #manycore #named #pipes and filters #self: Pipelets: self-organizing software pipelines for many-core architectures (JJ, JH), pp. 1516–1521.
DATE-2013-LeeKPK #approach: An integrated approach for managing the lifetime of flash-based SSDs (SL, TK, JP, JK), pp. 1522–1525.
DATE-2013-VenutoS: Dr. Frankenstein’s dream made possible: implanted electronic devices (DDV, ALSV), pp. 1531–1536.
DATE-2013-HoofP #health #smarttech: Addressing the healthcare cost dilemma by managing health instead of managing illness: an opportunity for wearable wireless sensors (CVH, JP), pp. 1537–1539.
DATE-2013-OlivoGCM #delivery #power management: Electronic implants: power delivery and management (JO, SSG, SC, GDM), pp. 1540–1545.
DATE-2013-KleefMLMTBSM #interface #multi: Cyborg insects, neural interfaces and other things: building interfaces between the synthetic and the multicellular (JVK, TM, PL, RM, RT, TB, HS, MMM), p. 1546.
DATE-2013-KondratyevLMW #evaluation #synthesis: Share with care: a quantitative evaluation of sharing approaches in high-level synthesis (AK, LL, MM, YW), pp. 1547–1552.
DATE-2013-Gomez-PradoCT #latency #optimisation #using: FPGA latency optimization using system-level transformations and DFG restructuring (DGP, MJC, RT), pp. 1553–1558.
DATE-2013-RutzigBC #configuration management #energy #framework #multi #platform: A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation (MBR, ACSB, LC), pp. 1559–1564.
DATE-2013-ChenLSCCAN #embedded #modelling #synthesis: High-level modeling and synthesis for embedded FPGAs (XC, SL, JS, TC, AC, GA, TGN), pp. 1565–1570.
DATE-2013-CastellanaF #analysis #independence #liveness #scheduling #synthesis: Scheduling independent liveness analysis for register binding in high level synthesis (VGC, FF), pp. 1571–1574.
DATE-2013-LeeJS #architecture #hybrid #memory management #performance: Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs (JL, YJ, SS), pp. 1575–1578.
DATE-2013-HanCL #compilation: Compiling control-intensive loops for CGRAs with state-based full predication (KH, KC, JL), pp. 1579–1582.
DATE-2013-JoseNKM #adaptation #named: DeBAR: deflection based adaptive router with minimal buffering (JJ, BN, DKK, MM), pp. 1583–1588.
DATE-2013-RaminiGBB #3d #analysis #manycore #power management #using: Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis (LR, PG, SB, DB), pp. 1589–1594.
DATE-2013-WachterEAM #fault tolerance: Topology-agnostic fault-tolerant NoC routing method (EW, AE, AMA, FM), pp. 1595–1600.
DATE-2013-EbrahimiDP #3d #algorithm #fault tolerance #using: Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy (ME, MD, JP), pp. 1601–1604.
DATE-2013-BanaiyanMofradDG #analysis #distributed #fault tolerance #modelling: Modeling and analysis of fault-tolerant distributed memories for networks-on-chip (AB, ND, GG), pp. 1605–1608.
DATE-2013-BouhadibaMM #energy #modelling #validation: System-level modeling of energy in TLM for early validation of power and thermal management (TB, MM, FM), pp. 1609–1614.
DATE-2013-ChenM #analysis #modelling #reliability: System-level modeling and microprocessor reliability analysis for backend wearout mechanisms (CCC, LM), pp. 1615–1620.
DATE-2013-AlieeGRT #analysis #automation #fault #reliability: Automatic success tree-based reliability analysis for the consideration of transient and permanent faults (HA, MG, FR, JT), pp. 1621–1626.
DATE-2013-SabooriA #embedded #hybrid #manycore #prototype: Hybrid prototyping of multicore embedded systems (ES, SA), pp. 1627–1630.
DATE-2013-DasKV13a #communication #design #energy #fault #manycore #migration: Communication and migration energy aware design space exploration for multicore systems with intermittent faults (AD, AK, BV), pp. 1631–1636.
DATE-2013-ParkQPC #embedded #logic #self: 40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS (SP, MQ, LSP, APC), pp. 1637–1642.
DATE-2013-WangYWZ #3d #configuration management #manycore #network: 3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors (KW, HY, BW, CZ), pp. 1643–1648.
DATE-2013-XydisPS #configuration management: Thermal-aware datapath merging for coarse-grained reconfigurable processors (SX, GP, CS), pp. 1649–1654.
DATE-2013-ZhouMS #locality #optimisation #power management: Placement optimization of power supply pads based on locality (PZ, VM, SSS), pp. 1655–1660.
DATE-2013-ZhaiYZ #algorithm #float #random: GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects (KZ, WY, HZ), pp. 1661–1666.
DATE-2013-TzouBHC #bound #composition #using: Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling (NT, DB, SWH, AC), pp. 1667–1672.
DATE-2013-KumarK #3d: Crosstalk avoidance codes for 3D VLSI (RK, SPK), pp. 1673–1678.
DATE-2013-Feng #geometry #grid #power management #reduction #scalability: Large-scale flip-chip power grid reduction with geometric templates (ZF), pp. 1679–1682.
DATE-2013-ChanCK #adaptation #scalability: Impact of adaptive voltage scaling on aging-aware signoff (TBC, WTJC, ABK), pp. 1683–1688.
DATE-2013-DaloukasMETS #approach #delivery #network #parallel #performance #power management: A parallel fast transform-based preconditioning approach for electrical-thermal co-simulation of power delivery networks (KD, AM, NEE, PT, GIS), pp. 1689–1694.
DATE-2013-RahimiBG #adaptation #approach: Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging (AR, LB, RKG), pp. 1695–1700.
DATE-2013-LiuLHCLL #clustering #effectiveness #linear #network #programming #prototype #statistics: Effective power network prototyping via statistical-based clustering and sequential linear programming (SYSL, CJL, CCH, HMC, CTL, CHL), pp. 1701–1706.
DATE-2013-LiuLC #algorithm: A network-flow based algorithm for power density mitigation at post-placement stage (SYSL, RGL, HMC), pp. 1707–1710.
DATE-2013-RayB #performance: An efficient wirelength model for analytical placement (BNBR, SB), pp. 1711–1714.
DATE-2013-YakovlevVR #industrial #logic #roadmap #tool support: Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools (AY, PV, MR), pp. 1715–1724.
DATE-2013-MockCRB #interactive #scalability: Interactions of large scale EV mobility and virtual power plants (RM, TSC, JR, LB), pp. 1725–1729.
DATE-2013-GreenGW #energy: Innovative energy storage solutions for future electromobility in smart cities (KG, SRG, RW), pp. 1730–1734.
DATE-2013-HankMVK #network: Automotive ethernet: in-vehicle networking and smart mobility (PH, SM, OV, JVdK), pp. 1735–1739.
DATE-2013-VermesanBJHBM #architecture #ecosystem #mobile: Smart, connected and mobile: architecting future electric mobility ecosystems (OV, LCJB, RJ, PH, RB, AM), pp. 1740–1744.
DATE-2013-ZafalonCV #industrial: e-Mobility the next frontier for automotive industry (RZ, GC, OV), pp. 1745–1748.
DATE-2013-JohnSVK: Semiconductor technologies for smart mobility management (RJ, MS, OV, KK), pp. 1749–1752.
DATE-2013-GaoBW #paradigm #performance: A new paradigm for trading off yield, area and performance to enhance performance per wafer (YG, MAB, YW), pp. 1753–1758.
DATE-2013-RehmanSAKCH #hardware #reliability: Leveraging variable function resilience for selective software reliability on unreliable hardware (SR, MS, PVA, FK, JJC, JH), pp. 1759–1764.
DATE-2013-JiangEP #embedded #optimisation #set: Optimization of secure embedded systems with dynamic task sets (KJ, PE, ZP), pp. 1765–1770.
DATE-2013-SchonwaldVBR #deployment #memory management: Shared memory aware MPSoC software deployment (TS, AV, OB, WR), pp. 1771–1776.
DATE-2013-YingHH #3d #performance: Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems (HY, TH, KH), pp. 1777–1782.
DATE-2013-TodorovMRS #approach #clustering #synthesis: A spectral clustering approach to application-specific network-on-chip synthesis (VT, DMG, HR, US), pp. 1783–1788.
DATE-2013-ChenRSIFC #analysis #process: A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
DATE-2013-PalitHNN #design #logic: Systematic design of nanomagnet logic circuits (IP, XSH, JN, MTN), pp. 1795–1800.
DATE-2013-SuR #logic: Defect-tolerant logic hardening for crossbar-based nanosystems (YS, WR), pp. 1801–1806.
DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using: On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.
DATE-2013-NoguchiNAFAKNMN #energy #hybrid #memory management #performance: D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory (HN, KN, KA, SF, EA, KK, TN, SM, HN), pp. 1813–1818.
DATE-2013-BoleyCAC #analysis #estimation #performance: Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN (JB, VC, RCA, BHC), pp. 1819–1824.
DATE-2013-VenkatesanSRR #energy #named #performance #using: DWM-TAPESTRI — an energy efficient all-spin cache using domain wall shift based writes (RV, MS, KR, AR), pp. 1825–1830.
DATE-2013-TuHC: Co-synthesis of data paths and clock control paths for minimum-period clock gating (WPT, SHH, CHC), pp. 1831–1836.
DATE-2013-LuL #multi: Slack budgeting and slack to length converting for multi-bit flip-flop merging (CCL, RBL), pp. 1837–1842.
DATE-2013-UnutulmazDF #optimisation #using: Area optimization on fixed analog floorplans using convex area functions (AU, GD, FVF), pp. 1843–1848.
DATE-2013-PanCL #agile #design #named #parallel #performance #search-based #towards: PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design (PCP, HMC, CCL), pp. 1849–1854.
DATE-2013-LivramentoGGJ #performance: Fast and efficient lagrangian relaxation-based discrete gate sizing (VSL, CG, JLG, MOJ), pp. 1855–1860.
DATE-2013-KahngLN #design #estimation #metamodelling #problem: Enhanced metamodeling techniques for high-dimensional IC design estimation problems (ABK, BL, SN), pp. 1861–1866.
DATE-2013-Struzyna #polynomial: Sub-quadratic objectives in quadratic placement (MS), pp. 1867–1872.
DATE-2013-WeiLSHAS #design #effectiveness #named: CATALYST: planning layer directives for effective design closure (YW, ZL, CCNS, SH, CJA, SSS), pp. 1873–1878.
DATE-2013-ElfadelMA #formal method #industrial #manycore: Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice (IME, RM, DA), pp. 1879–1881.

Enrico MaciiProceedings of the 17th Conference on Design, Automation and Test in EuropeDATE, 2013.

Contents (359 items)

Enrico Macii
Proceedings of the 17th Conference on Design, Automation and Test in Europe
DATE, 2013.