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Travelled to:
1 × Germany
2 × USA
Collaborated with:
J.Yang L.N.Bhuyan J.Yao Y.Luo W.Wu X.Chen H.Hsieh F.Balarin
Talks about:
processor (3) network (3) design (2) architectur (1) bipartit (1) program (1) recurs (1) explor (1) assert (1) refin (1)

Person: Jia Yu

DBLP DBLP: Yu:Jia

Contributed to:

DAC 20072007
DAC 20052005
DATE 20052005

Wrote 3 papers:

DAC-2007-YuYBY #clustering #network #recursion
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining (JY, JY, LNB, JY), pp. 805–810.
DAC-2005-LuoYYB #design #network #power management #using
Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
DATE-2005-YuWCHYB #architecture #design #network
Assertion-Based Design Exploration of DVS in Network Processor Architectures (JY, WW, XC, HH, JY, FB), pp. 92–97.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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