Low power network processor design using clock gating
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Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
Low power network processor design using clock gating
DAC, 2005.

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@inproceedings{DAC-2005-LuoYYB,
	author        = "Yan Luo and Jia Yu and Jun Yang and Laxmi N. Bhuyan",
	booktitle     = "{Proceedings of the 42nd Design Automation Conference}",
	doi           = "10.1145/1065579.1065766",
	isbn          = "1-59593-058-2",
	pages         = "712--715",
	publisher     = "{ACM}",
	title         = "{Low power network processor design using clock gating}",
	year          = 2005,
}

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