Travelled to:1 × Canada
1 × France
7 × USA
Collaborated with:J.Kuang G.Liao R.Gupta J.Yu J.Yang R.R.Iyer Y.Luo R.Klefstad M.Feng X.Zhu H.Yu M.Pirvu N.Ni F.Khorasani K.Vora J.Yao X.Chen H.Hsieh F.Balarin
Talks about:network (5) processor (3) process (2) perform (2) system (2) switch (2) server (2) latenc (2) design (2) power (2)
Person: Laxmi N. Bhuyan
DBLP: Bhuyan:Laxmi_N=
Contributed to:
2014
2012
2012
2011201020072005
20041999Wrote 11 papers:
- HPDC-2014-KhorasaniVGB #graph #named
- CuSha: vertex-centric graph processing on GPUs (FK, KV, RG, LNB), pp. 239–252.
- DAC-2012-KuangBK #manycore #network #optimisation
- Traffic-aware power optimization for network applications on multicore servers (JK, LNB, RK), pp. 1006–1011.
- PPoPP-2012-FengGB #parallel
- Speculative parallelization on GPGPUs (MF, RG, LNB), pp. 293–294.
- HPCA-2011-LiaoZB #architecture #network
- A new server I/O architecture for high speed networks (GL, XZ, LNB), pp. 255–265.
- DAC-2010-KuangB #latency #named
- LATA: a latency and throughput-aware packet processing system (JK, LNB), pp. 36–41.
- DAC-2010-LiaoYB #performance
- A new IP lookup cache for high performance IP routers (GL, HY, LNB), pp. 338–343.
- DAC-2007-YuYBY #clustering #network #recursion
- Program Mapping onto Network Processors by Recursive Bipartitioning and Refining (JY, JY, LNB, JY), pp. 805–810.
- DAC-2005-LuoYYB #design #network #power management #using
- Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
- DATE-DF-2004-ChenLHBB #design #network
- Utilizing Formal Assertions for System Design of Network Processors (XC, YL, HH, LNB, FB), pp. 126–133.
- HPCA-1999-IyerB #framework #latency #memory management #multi
- Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors (RRI, LNB), pp. 152–160.
- HPCA-1999-PirvuBN #performance
- The Impact of Link Arbitration on Switch Performance (MP, LNB, NN), pp. 228–235.