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Travelled to:
1 × USA
Collaborated with:
S.Huang K.Cheng K.Chen
Talks about:
sequenti (1) diagnosi (1) circuit (1) design (1) simul (1) fault (1) error (1) base (1)

Person: Juin-Yeu Joseph Lu

DBLP DBLP: Lu:Juin=Yeu_Joseph

Contributed to:

DAC 19981998

Wrote 1 papers:

DAC-1998-HuangCCL #design #fault
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits (SYH, KTC, KCC, JYJL), pp. 632–637.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.