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Travelled to:
1 × France
2 × USA
Collaborated with:
M.Wachs M.Horowitz J.P.Stevenson S.Richardson A.Danowitz P.Stevenson S.Richardon A.Solomatnikov A.Firoozshahian W.Qadeer O.Shacham Z.Asgar R.Hameed
Talks about:
generat (2) chip (2) represent (1) processor (1) intermedi (1) overhead (1) interfac (1) control (1) remov (1) multi (1)

Person: Kyle Kelley

DBLP DBLP: Kelley:Kyle

Contributed to:

DAC 20122012
DATE 20112011
DAC 20072007

Wrote 3 papers:

DAC-2012-KelleyWSRH #interface
Removing overhead from high-level interfaces (KK, MW, JPS, SR, MH), pp. 783–789.
DATE-2011-KelleyWDSRH #generative
Intermediate representations for controllers in chip generators (KK, MW, AD, PS, SR, MH), pp. 1394–1399.
DAC-2007-SolomatnikovFQSKAWHH #generative #multi
Chip Multi-Processor Generator (AS, AF, WQ, OS, KK, ZA, MW, RH, MH), pp. 262–263.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.