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Travelled to:
1 × France
3 × USA
Collaborated with:
M.Horowitz D.Ip K.Kelley S.Richardson A.Danowitz O.Shacham W.Qadeer J.P.Stevenson P.Stevenson S.Richardon A.Solomatnikov A.Firoozshahian Z.Asgar R.Hameed S.Galal S.Sankaranarayanan J.Brunhaver A.Vassiliev
Talks about:
generat (2) design (2) level (2) chip (2) represent (1) processor (1) intermedi (1) overhead (1) interfac (1) challeng (1)

Person: Megan Wachs

DBLP DBLP: Wachs:Megan

Contributed to:

DAC 20152015
DAC 20122012
DATE 20112011
DAC 20072007

Wrote 5 papers:

DAC-2015-WachsI #challenge #design #hardware #integration #security
Design and integration challenges of building security hardware IP (MW, DI), p. 6.
DAC-2012-KelleyWSRH #interface
Removing overhead from high-level interfaces (KK, MW, JPS, SR, MH), pp. 783–789.
DAC-2012-ShachamGSWBVHDQR #design #game studies
Avoiding game over: bringing design to the next level (OS, SG, SS, MW, JB, AV, MH, AD, WQ, SR), pp. 623–629.
DATE-2011-KelleyWDSRH #generative
Intermediate representations for controllers in chip generators (KK, MW, AD, PS, SR, MH), pp. 1394–1399.
DAC-2007-SolomatnikovFQSKAWHH #generative #multi
Chip Multi-Processor Generator (AS, AF, WQ, OS, KK, ZA, MW, RH, MH), pp. 262–263.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.