BibSLEIGH — Mark

Travelled to:

1 × France
1 × Germany
15 × USA

Collaborated with:

D.Stark J.Kim M.D.Smith M.Wachs M.Jeeradit ∅ J.Solomon J.P.Bergmann H.Kapadia A.Salz C.W.Carpenter Mingyu Gao Jing Pu Xuan Yang C.Kozyrakis K.Kelley D.Lie C.A.Thekkath A.Gupta J.P.Stevenson S.Youn J.Laudon M.S.Lam M.Johnson S.Richardson A.Danowitz F.O'Mahony C.P.Yue S.S.Wong S.G.Govindaraju D.L.Dill A.J.Hu O.Shacham W.Qadeer O.Azizi A.Mahesri S.J.Patel P.Stevenson S.Richardon F.Lau S.Liao B.Lim J.Mao D.Densmore S.Krishnaswamy X.Shen A.Arkin E.Winfree C.Voigt M.Mitchell P.Lincoln D.Boneh J.C.Mitchell A.Solomatnikov A.Firoozshahian Z.Asgar R.Hameed J.M.Rabaey D.Sylvester D.Blaauw K.Bernstein J.Frenkil W.Nebel T.Sakurai A.Yang S.Galal S.Sankaranarayanan J.Brunhaver A.Vassiliev Qiaoyi Liu Jeff Setter Ankita Nayak Steven Bell Kaidi Cao Heonjae Ha Priyanka Raina M.Heinrich J.Kuskin D.Ofelt J.Heinlein J.Baxter J.P.Singh R.Simoni K.Gharachorloo D.Nakahira M.Rosenblum J.L.Hennessy

Talks about:

design (7) use (6) network (3) generat (3) circuit (3) acceler (3) level (3) multiprocessor (2) increment (2) scalabl (2)

Person: Mark Horowitz

DBLP: Horowitz:Mark

Contributed to:

2012

2011

2010

2007

2003

2001

2000

1999

1998

1994

1992

1989

1988

1987

2017

2019

2020

Wrote 29 papers:

DAC-2012-KelleyWSRH #interface: Removing overhead from high-level interfaces (KK, MW, JPS, SR, MH), pp. 783–789.
DAC-2012-ShachamGSWBVHDQR #design #game studies: Avoiding game over: bringing design to the next level (OS, SG, SS, MW, JB, AV, MH, AD, WQ, SR), pp. 623–629.
DAC-2011-DensmoreHKSAWV #biology #design #synthesis: Joint DAC/IWBDA special session design and synthesis of biological circuits (DD, MH, SK, XS, AA, EW, CV), pp. 114–115.
DAC-2011-YounKH #analysis #convergence: Global convergence analysis of mixed-signal systems (SY, JK, MH), pp. 498–503.
DATE-2011-KelleyWDSRH #generative: Intermediate representations for controllers in chip generators (KK, MW, AD, PS, SR, MH), pp. 1394–1399.
DAC-2010-HorowitzJLLLM #analysis #equivalence #modelling: Fortifying analog models with equivalence checking and coverage analysis (MH, MJ, FL, SL, BL, JM), pp. 425–430.
DATE-2010-AziziMSPH #architecture #design #framework: An integrated framework for joint design space exploration of microarchitecture and circuits (OA, AM, JPS, SJP, MH), pp. 250–255.
DATE-2010-Horowitz #design #why: Why design must change: Rethinking digital design (MH), p. 791.
DATE-2010-JeeraditKH #optimisation: Intent-leveraged optimization of analog circuits via homotopy (MJ, JK, MH), pp. 1614–1619.
DAC-2007-SolomatnikovFQSKAWHH #generative #multi: Chip Multi-Processor Generator (AS, AF, WQ, OS, KK, ZA, MW, RH, MH), pp. 262–263.
DAC-2003-OMahonyYHW #design #network #using: Design of a 10GHz clock distribution network using coupled standing-wave oscillators (FO, CPY, MH, SSW), pp. 682–687.
DAC-2003-RabaeySBBFHNSY: Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
SOSP-2003-LieTH #hardware #implementation #operating system: Implementing an untrusted operating system on trusted hardware (DL, CAT, MH), pp. 178–192.
DAC-2001-SolomonH #layout #using: Using Texture Mapping with Mipmapping to Render a VLSI Layout (JS, MH), pp. 500–505.
ASPLOS-2000-LieTMLBMH #architecture: Architectural Support for Copy and Tamper Resistant Software (DL, CAT, MM, PL, DB, JCM, MH), pp. 168–177.
DAC-1999-BergmannH #named: Vex — A CAD Toolbox (JPB, MH), pp. 523–528.
DAC-1999-KapadiaH #automation #clustering #convergence #design #standard #using: Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology (HK, MH), pp. 592–597.
DAC-1998-GovindarajuDHH #approximate #reachability #using: Approximate Reachability with BDDs Using Overlapping Projections (SGG, DLD, AJH, MH), pp. 451–456.
ASPLOS-1994-HeinrichKOHBSSGNHGRH #flexibility #multi #performance: The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor (MH, JK, DO, JH, JB, JPS, RS, KG, DN, MH, AG, MR, JLH), pp. 274–285.
ASPLOS-1994-LaudonGH #multi #named #thread: Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations (JL, AG, MH), pp. 308–318.
ASPLOS-1992-SmithHL #performance: Efficient Superscalar Performance Through Boosting (MDS, MH, MSL), pp. 248–259.
ASPLOS-1989-SmithJH #multi: Limits on Multiple Instruction Issue (MDS, MJ, MH), pp. 290–302.
DAC-1989-SalzH #incremental #named: IRSIM: An Incremental MOS Switch-Level Simulator (AS, MH), pp. 173–178.
DAC-1988-StarkH #network #power management #using: Analyzing CMOS Power Supply Networks Using Ariel (DS, MH), pp. 460–464.
DAC-1987-CarpenterH #constraints #generative #incremental: Generating Incremental VLSI Compaction Spacing Constraints (CWC, MH), pp. 291–297.
DAC-1987-StarkH #named #simulation: RED: Resistance Extraction for Digital Simulation (DS, MH), pp. 570–573.
ASPLOS-2017-GaoPYHK #3d #memory management #named #network #performance #scalability: TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (MG, JP, XY, MH, CK), pp. 751–764.
ASPLOS-2019-GaoYPHK #data flow #named #scalability: TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators (MG, XY, JP, MH, CK), pp. 807–820.
ASPLOS-2020-YangGLSPNBCHRKH #named #scheduling #using: Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators (XY, MG, QL, JS, JP, AN, SB, KC, HH, PR, CK, MH), pp. 369–383.