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Travelled to:
1 × France
Collaborated with:
J.Constantin G.Karakonstantis A.Chattopadhyay A.Burg
Talks about:
microprocessor (1) instruct (1) frequenc (1) exploit (1) margin (1) adjust (1) scale (1) dynam (1) clock (1) time (1)

Person: Lai Wang

DBLP DBLP: Wang:Lai

Contributed to:

DATE 20152015

Wrote 1 papers:

DATE-2015-ConstantinWKCB
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment (JC, LW, GK, AC, AB), pp. 381–386.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.