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Travelled to:
1 × Austria
1 × France
1 × USA
2 × Germany
Collaborated with:
R.Martens H.D.Man S.Hendricx P.Odent S.Perremans I.Bolsens W.D.Rammelaere P.Six J.M.Rabaey
Talks about:
signatur (3) verif (3) dynam (3) line (3) circuit (2) analysi (2) formal (2) time (2) multiprocessor (1) verificatio (1)

Person: Luc J. M. Claesen

DBLP DBLP: Claesen:Luc_J=_M=

Contributed to:

DATE 19991999
ED&TC 19971997
ICDAR 19971997
ICPR 19961996
DAC 19891989
DAC 19861986

Wrote 9 papers:

Formally Verified Redundancy Removal (SH, LJMC), p. 150–?.
EDTC-1997-HendricxC #approach #verification
A symbolic core approach to the formal verification of integrated mixed-mode applications (SH, LJMC), pp. 432–436.
ICDAR-1997-MartensC #online #optimisation #programming
Dynamic Programming Optimisation for On-line Signature Verificatio (RM, LJMC), pp. 653–656.
ICDAR-1997-MartensC97a #online #verification
On-line Signature Verification: Discrimination Emphasised (RM, LJMC), pp. 657–660.
ICPR-1996-MartensC #online #verification
On-line signature verification by dynamic time-warping (RM, LJMC), pp. 38–42.
DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.
DAC-1989-OdentCM #feedback #implementation #multi #scalability
Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator (PO, LJMC, HDM), pp. 25–30.
DAC-1989-PerremansCM #analysis
Static Timing Analysis of Dynamically Sensitizable Paths (SP, LJMC, HDM), pp. 568–573.
DAC-1986-SixCRM #generative
An intelligent module generator environment (PS, LJMC, JMR, HDM), pp. 730–735.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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