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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
R.Vemuri S.Govindarajan I.Ouaiss
Talks about:
reconfigur (3) tempor (3) partit (3) synthesi (2) design (2) architectur (1) approach (1) fission (1) latenc (1) explor (1)

Person: Meenakshi Kaul

DBLP DBLP: Kaul:Meenakshi

Contributed to:

DAC 19991999
DATE 19991999
DATE 19981998

Wrote 3 papers:

DAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.
DATE-1999-KaulV #clustering #design #latency #runtime
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs (MK, RV), pp. 202–209.
DATE-1998-KaulV #architecture #clustering #configuration management #synthesis
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures (MK, RV), pp. 389–396.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.