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Travelled to:
1 × France
Collaborated with:
S.Miryala A.Calimera E.Macii M.Poncino
Talks about:
reconfigur (1) junction (1) verilog (1) graphen (1) model (1) logic (1) gate (1) base (1)

Person: Mehrdad Montazeri

DBLP DBLP: Montazeri:Mehrdad

Contributed to:

DATE 20132013

Wrote 1 papers:

DATE-2013-MiryalaMCMP #configuration management #logic
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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