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Travelled to:
2 × USA
4 × France
4 × Germany
Collaborated with:
E.Macii M.Poncino A.Macii V.Tenace L.Benini S.Miryala S.Rinaudo M.Loghi M.Montazeri G.Gangemi W.Liu A.Nannarelli L.M.V.Bolzani A.V.Sathanur A.Sassone R.Goldman V.Melikyan E.Babayan
Talks about:
logic (5) graphen (4) power (4) base (4) design (3) pass (3) temperatur (2) constraint (2) distribut (2) junction (2)

Person: Andrea Calimera

DBLP DBLP: Calimera:Andrea

Contributed to:

DAC 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DATE 20112011
DATE 20102010
DATE 20092009
DATE 20082008
DATE 20072007

Wrote 12 papers:

DAC-2015-TenaceCMP #logic #synthesis
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
DATE-2014-TenaceCMP #logic
Pass-XNOR logic: A new logic style for P-N junction based graphene circuits (VT, AC, EM, MP), pp. 1–4.
DAC-2013-CalimeraMP #constraints #energy #fault #scheduling
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.
DATE-2013-MiryalaMCMP #configuration management #logic
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
DATE-2012-MiryalaCMP #analysis #network
IR-drop analysis of graphene-based power distribution networks (SM, AC, EM, MP), pp. 81–86.
DATE-2012-SassoneCMMPGMBR #dependence #network
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.
DATE-2011-CalimeraLMP #architecture
Partitioned cache architectures for reduced NBTI-induced aging (AC, ML, EM, MP), pp. 938–943.
DATE-2011-RinaudoGCMP #approach #design #energy #performance #power management
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems (SR, GG, AC, AM, MP), pp. 1127–1128.
DATE-2010-LiuNCMP #reduction
Post-placement temperature reduction techniques (WL, AN, AC, EM, MP), pp. 634–637.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management
Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2008-CalimeraBM #constraints #performance #power management
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints (AC, LB, EM), pp. 973–978.
DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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