BibSLEIGH — Enrico

Travelled to:

1 × Japan
11 × France
14 × USA
8 × Germany

Collaborated with:

M.Poncino L.Benini A.Macii A.Calimera F.Somenzi G.D.Hachtel G.D.Micheli P.Babighian R.Scarsi L.Macchiarulo M.Loghi D.Shin A.Pardo H.Cho H.Mahmood F.Fummi A.V.Sathanur V.Tenace M.Pedram A.Ivaldi A.Acquaviva S.Miryala F.Ferrandi R.Zafalon D.Sciuto A.Pullini G.Odasso R.I.Bahar K.Patel G.Castelli E.Patti S.Rinaudo S.D.Cataldo A.Bottino E.Ficarra B.Stefano D.Bertozzi O.Golubeva M.Donno F.Crudo D.Bruni B.Kumthekar A.Sassone G.Ayad B.Sahbi R.Lemaire M.Montazeri W.Liu A.Nannarelli L.M.V.Bolzani C.Silvano B.Plessier A.Chakraborty P.Sithambaram K.Duraisami D.Friebel R.C.Aitken A.Domic E.Omerbegovic F.Pro A.Lioy F.G.Brundu M.Grosso G.Rasconà S.Manne V.Guarnieri M.Petricca S.Vinco N.Bombieri F.Abate A.Osello A.Cocuccio M.Jahn M.Jentsch R.Goldman V.Melikyan E.Babayan G.Kamhi S.Miller S.B.Mentor W.Nebel Y.C.Wong J.Karmann S.V.Kosonocky S.Curtis

Talks about:

power (21) optim (13) energi (10) base (10) design (9) gate (8) algorithm (7) memori (7) clock (7) awar (7)

Person: Enrico Macii

DBLP: Macii:Enrico

Facilitated 1 volumes:

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

1994

1993

Wrote 60 papers:

DAC-2015-TenaceCMP #logic #synthesis: One-pass logic synthesis for graphene-based Pass-XNOR logic circuits (VT, AC, EM, MP), p. 6.
DATE-2015-BrunduPAGRRM #distributed #energy #framework #integration #strict: A new distributed framework for integration of district energy data from heterogeneous devices (FGB, EP, AA, MG, GR, SR, EM), pp. 992–993.
DAC-2014-ShinMP #modelling #statistics: Statistical Battery Models and Variation-Aware Battery Management (DS, EM, MP), p. 6.
DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification: A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
DATE-2014-MahmoodPM #performance #reduction #using: Cache aging reduction with improved performance using dynamically re-sizable cache (HM, MP, EM), pp. 1–6.
DATE-2014-ShinPM #architecture #hybrid #using: Thermal management of batteries using a hybrid supercapacitor architecture (DS, MP, EM), pp. 1–6.
DATE-2014-TenaceCMP #logic: Pass-XNOR logic: A new logic style for P-N junction based graphene circuits (VT, AC, EM, MP), pp. 1–4.
DAC-2013-CalimeraMP #constraints #energy #fault #scheduling: Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.
DATE-2013-AyadAMSL #energy #integration #variability: HW-SW integration for energy-efficient/variability-aware computing (GA, AA, EM, BS, RL), pp. 607–611.
DATE-2013-MiryalaMCMP #configuration management #logic: A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.
DATE-2012-MahmoodPLM #clustering #energy #memory management #optimisation: Application-specific memory partitioning for joint energy and lifetime optimization (HM, MP, ML, EM), pp. 364–369.
DATE-2012-MiryalaCMP #analysis #network: IR-drop analysis of graphene-based power distribution networks (SM, AC, EM, MP), pp. 81–86.
DATE-2012-PattiAAOCJJM #energy #middleware #network #performance: Middleware services for network interoperability in smart energy efficient buildings (EP, AA, FA, AO, AC, MJ, MJ, EM), pp. 338–339.
DATE-2012-SassoneCMMPGMBR #dependence #network: Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks (AS, AC, AM, EM, MP, RG, VM, EB, SR), pp. 165–166.
ICPR-2012-CataldoBFM #classification #image: Applying textural features to the classification of HEp-2 cell patterns in IIF images (SDC, AB, EF, EM), pp. 3349–3352.
DATE-2011-CalimeraLMP #architecture: Partitioned cache architectures for reduced NBTI-induced aging (AC, ML, EM, MP), pp. 938–943.
DATE-2010-LiuNCMP #reduction: Post-placement temperature reduction techniques (WL, AN, AC, EM, MP), pp. 634–637.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management: Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2009-SathanurPBMM #clustering #design #variability: Physically clustered forward body biasing for variability compensation in nanometer CMOS design (AVS, AP, LB, GDM, EM), pp. 154–159.
DATE-2008-CalimeraBM #constraints #performance #power management: Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints (AC, LB, EM), pp. 973–978.
DATE-2008-SathanurPBMMP #algorithm #framework #scalability: A Scalable Algorithmic Framework for Row-Based Power-Gating (AVS, AP, LB, AM, EM, MP), pp. 379–384.
DATE-2008-StefanoBBM #design #multi #pipes and filters #process: Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style (BS, DB, LB, EM), pp. 967–972.
DAC-2007-KamhiMMNWKMKC #design #power management #question #validation: Early Power-Aware Design & Validation: Myth or Reality? (GK, SM, SBM, WN, YCW, JK, EM, SVK, SC), pp. 210–211.
DATE-2007-GolubevaLPM #architecture: Architectural leakage-aware management of partitioned scratchpad memories (OG, ML, MP, EM), pp. 1665–1670.
DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.
DATE-2006-BabighianBMM: Enabling fine-grain leakage management by voltage anchor insertion (PB, LB, AM, EM), pp. 868–873.
DATE-2006-ChakrabortySDMMP #bound #optimisation: Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.
DATE-2006-MaciiPFADZ #design #matter #power management #question #tool support: Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATE-v1-2004-BabighianBM #algorithm #scalability: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (PB, LB, EM), pp. 500–505.
DATE-v1-2004-BabighianBM04a #distributed: Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PB, LB, EM), pp. 720–723.
DATE-v1-2004-BeniniIMM #design #memory management #metaprogramming: Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning (LB, AI, AM, EM), pp. 698–699.
DATE-v1-2004-PatelMP #architecture #energy #memory management #multi #synthesis: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC (KP, EM, MP), pp. 700–701.
DAC-2003-BeniniMMOPP #analysis #design #difference #energy: Energy-aware design techniques for differential power analysis protection (LB, AM, EM, EO, FP, MP), pp. 36–41.
DAC-2003-DonnoIBM #optimisation: Clock-tree power optimization based on RTL clock-gating (MD, AI, LB, EM), pp. 622–627.
DATE-2003-MaciiMCZ #algorithm #embedded #energy: A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.
DATE-2003-MaciiMP #clustering #memory management #performance: Improving the Efficiency of Memory Partitioning by Address Clustering (AM, EM, MP), pp. 10018–10023.
DATE-2002-BeniniBMM #embedded #energy: Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors (LB, DB, AM, EM), pp. 449–453.
DATE-2002-MacchiaruloMP #energy: Wire Placement for Crosstalk Energy Minimization in Address Buses (LM, EM, MP), pp. 158–162.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DATE-2001-BeniniCMMPS #scheduling: Extending lifetime of portable systems by battery scheduling (LB, GC, AM, EM, MP, RS), pp. 197–203.
DATE-2001-MacchiaruloBM #generative #layout #on the fly: On-the-fly layout generation for PTL macrocells (LM, LB, EM), pp. 546–551.
DAC-2000-BeniniMMP #embedded #optimisation #synthesis: Synthesis of application-specific memories for power optimization in embedded systems (LB, AM, EM, MP), pp. 300–303.
DATE-2000-BeniniCMMPS #estimation: A Discrete-Time Battery Model for High-Level Power Estimation (LB, GC, AM, EM, MP, RS), pp. 35–39.
DAC-1999-BeniniMMOP #algorithm #approximate #component #kernel #optimisation: Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (LB, GDM, EM, GO, MP), pp. 247–252.
DAC-1999-BeniniMMPS #communication #interface #power management #synthesis: Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DATE-1999-BeniniMMMPS #power management: Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DAC-1998-BeniniMLMOP #kernel #optimisation: Computational Kernels and their Application to Sequential Power Optimization (LB, GDM, AL, EM, GO, MP), pp. 764–769.
DAC-1998-KumthekarBMS #optimisation: In-Place Power Optimization for LUT-Based FPGAs (BK, LB, EM, FS), pp. 718–721.
DATE-1998-BeniniMSMS #encoding #optimisation: Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.
DATE-1998-FerrandiFMP #behaviour #estimation: Power Estimation of Behavioral Descriptions (FF, FF, EM, MP), pp. 762–766.
DAC-1997-BeniniMP #adaptation #design #latency #pipes and filters #throughput: Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control (LB, EM, MP), pp. 22–27.
DAC-1997-MaciiPS #estimation #modelling #optimisation: High-Level Power Modeling, Estimation, and Optimization (EM, MP, FS), pp. 504–511.
EDTC-1997-BeniniMMPS #logic #network #optimisation #synthesis: Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks (LB, GDM, EM, MP, RS), pp. 514–520.
DAC-1996-FerrandiFMPS #automaton #network #optimisation: Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques (FF, FF, EM, MP, DS), pp. 467–470.
DAC-1995-MannePBHSMP: Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.
DAC-1994-HachtelMPS #analysis #finite #probability #scalability #state machine: Probabilistic Analysis of Large Finite State Machines (GDH, EM, AP, FS), pp. 270–275.
EDAC-1994-BaharCHMS #analysis #using: Timing Analysis of Combinational Circuits using ADD’s (RIB, HC, GDH, EM, FS), pp. 625–629.
EDAC-1994-ChoHMPS #algorithm #approximate #automaton #composition #traversal: A State Space Decomposition Algorithm for Approximate FSM Traversal (HC, GDH, EM, MP, FS), pp. 137–141.
EDAC-1994-HachtelMPS #algorithm #finite #state machine: Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine (GDH, EM, AP, FS), pp. 214–218.
DAC-1993-ChoHMPS #algorithm #approximate #automaton #traversal: Algorithms for Approximate FSM Traversal (HC, GDH, EM, BP, FS), pp. 25–30.