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Travelled to:
1 × France
1 × Germany
1 × USA
Collaborated with:
Q.Tang A.Zjajo N.v.d.Meijs A.Nigam
Talks about:
transistor (2) statist (2) analysi (2) model (2) level (2) time (2) gate (2) base (2) uncertainti (1) waveform (1)

Person: Michel Berkelaar

DBLP DBLP: Berkelaar:Michel

Contributed to:

DATE 20122012
DATE 20112011
DAC 20102010

Wrote 3 papers:

DATE-2012-TangZBM #analysis #correlation #modelling #statistics
Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.
DATE-2011-NigamTZBM #nondeterminism #pseudo #representation
Pseudo circuit model for representing uncertainty in waveforms (AN, QT, AZ, MB, NvdM), pp. 1521–1524.
DAC-2010-TangZBM #analysis #simulation #statistics
RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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