Travelled to:1 × USA
2 × France
2 × Germany
Collaborated with:J.P.d.Gyvez Q.Tang M.Berkelaar N.v.d.Meijs S.S.Kumar R.v.Leuken M.J.B.Asian A.Nigam
Talks about:analysi (3) level (3) transistor (2) statist (2) circuit (2) static (2) integr (2) analog (2) simul (2) model (2)
Person: Amir Zjajo
DBLP: Zjajo:Amir
Contributed to:
2015
20122011
201020082007Wrote 6 papers:
- PDP-2015-KumarZL #framework #named
- Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip (SSK, AZ, RvL), pp. 674–681.
- DATE-2012-TangZBM #analysis #correlation #modelling #statistics
- Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.
- DATE-2011-NigamTZBM #nondeterminism #pseudo #representation
- Pseudo circuit model for representing uncertainty in waveforms (AN, QT, AZ, MB, NvdM), pp. 1521–1524.
- DAC-2010-TangZBM #analysis #simulation #statistics
- RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.
- DATE-2008-ZjajoG #analysis #fault #multi
- Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters (AZ, JPdG), pp. 74–79.
- DATE-2007-ZjajoAG #interactive #monitoring #parametricity #process
- Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits (AZ, MJBA, JPdG), pp. 1301–1306.