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Travelled to:
1 × Portugal
2 × Germany
Collaborated with:
S.Ciraci M.Monchiero G.Palermo C.Silvano P.Schaumont I.Verbauwhede
Talks about:
multiprocessor (1) framework (1) synchron (1) perform (1) hardwar (1) generat (1) exploit (1) system (1) serial (1) memori (1)

Person: Oreste Villa

DBLP DBLP: Villa:Oreste

Contributed to:

SAC 20132013
DATE 20062006
DATE 20052005

Wrote 3 papers:

SAC-2013-CiraciV #code generation #points-to
Exploiting points-to maps for de-/serialization code generation (SC, OV), pp. 1712–1719.
DATE-2006-MonchieroPSV #hardware #optimisation #performance
Power/performance hardware optimization for synchronization intensive applications in MPSoCs (MM, GP, CS, OV), pp. 606–611.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance
Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.