Travelled to:1 × France
Collaborated with:P.Magarshack G.Cesana E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart S.Bernard G.Moritz O.Billoint Y.Maneglia J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:design (2) breakthrough (1) symbiosi (1) silicon (1) process (1) voltag (1) energi (1) effici (1) deplet (1) ultra (1)
Person: Philippe Flatresse
DBLP: Flatresse:Philippe
Contributed to:
2013Wrote 2 papers:
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
- DATE-2013-MagarshackFC #design #energy #process
- UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency (PM, PF, GC), pp. 952–957.