Travelled to:2 × France
Collaborated with:H.Sarhan I.Rayane M.Vinet P.Batude C.Fenouillet-Béranger O.Rozeau G.Cibrario F.Deprat A.Fustier J.Michallet O.Faynot O.Turkyilmaz J.Christmann S.Thuries F.Clermidy E.Beigné A.Valentian B.Giraud O.Thomas T.Benoist Y.Thonnart S.Bernard G.Moritz Y.Maneglia P.Flatresse J.Noël F.Abouzeid B.Pelloux-Prayer A.Grover S.Clerc P.Roche J.L.Coz S.Engels R.Wilson
Talks about:design (2) cell (2) comprehens (1) monolith (1) commerci (1) silicon (1) voltag (1) deplet (1) ultra (1) studi (1)
Person: Olivier Billoint
DBLP: Billoint:Olivier
Contributed to:
20152013Wrote 2 papers:
- DATE-2015-BillointSRVBFRC #2d #3d #design #using
- A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool (OB, HS, IR, MV, PB, CFB, OR, GC, FD, AF, JM, OF, OT, JFC, ST, FC), pp. 1192–1196.
- DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design
- Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.