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Travelled to:
1 × France
2 × Germany
Collaborated with:
M.H.Zaki S.Tahar A.Daghar B.Akbarpour L.C.Paulson
Talks about:
analog (3) process (2) presenc (2) circuit (2) variat (2) nois (2) use (2) pattern (1) correct (1) verifi (1)

Person: Rajeev Narayanan

DBLP DBLP: Narayanan:Rajeev

Contributed to:

DATE 20122012
DATE 20112011
DATE 20102010

Wrote 3 papers:

DATE-2012-NarayananDZT #design #using #verification
Verifying jitter in an analog and mixed signal design using dynamic time warping (RN, AD, MHZ, ST), pp. 1413–1416.
DATE-2011-NarayananZT #correctness #pattern matching #process #using
Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching (RN, MHZ, ST), pp. 1188–1191.
DATE-2010-NarayananAZTP #process #verification
Formal verification of analog circuits in the presence of noise and process variation (RN, BA, MHZ, ST, LCP), pp. 1309–1312.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.