Travelled to:1 × Australia
1 × Canada
1 × Finland
1 × The Netherlands
1 × United Kingdom
2 × France
2 × USA
8 × Germany
Collaborated with:M.H.Zaki O.Hasan A.Habibi R.Narayanan B.Akbarpour N.Abbasi U.Siddique J.B.Hassen O.A.Mohamed O.Lahiouel H.Aridhi G.A.Sammane H.Moinudeen A.T.Abdel-Hamid E.M.Aboulhamid A.Gawanmeh K.Winter A.Dekdouk M.Nayrolles A.Hamou-Lhadj A.Larsson A.Daghar A.I.Ahmed H.Xiong P.Curzon A.Blandford L.C.Paulson R.Akbarpour A.Samarah D.Li K.D.Anon N.Boulerice E.Cerny F.Corella M.Langevin X.Song Y.Xu Z.Zhou
Talks about:verif (9) formal (8) use (8) design (7) analog (6) system (5) circuit (4) base (4) mdg (4) probabilist (3)
Person: Sofiène Tahar
DBLP: Tahar:Sofi=egrave=ne
Contributed to:
2015
2015
2014201220112010
2009
2009
2007200720072006200620052004
20032002
1996Wrote 22 papers:
- DAC-2015-LahiouelZT #smt #towards #using
- Towards enhancing analog circuits sizing using SMT-based techniques (OL, MHZ, ST), p. 6.
- SANER-2015-NayrollesHTL #approach #debugging #model checking #named #using
- JCHARMING: A bug reproduction approach using crash traces and directed model checking (MN, AHL, ST, AL), pp. 101–110.
- DATE-2014-SiddiqueT #analysis #formal method #towards
- Towards the formal analysis of microresonators based photonic systems (US, ST), pp. 1–6.
- DATE-2012-AridhiZT #order #reduction #simulation #towards #using
- Towards improving simulation of analog circuits using model order reduction (HA, MHZ, ST), pp. 1337–1342.
- DATE-2012-NarayananDZT #design #using #verification
- Verifying jitter in an analog and mixed signal design using dynamic time warping (RN, AD, MHZ, ST), pp. 1413–1416.
- DATE-2011-NarayananZT #correctness #pattern matching #process #using
- Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching (RN, MHZ, ST), pp. 1188–1191.
- DATE-2010-NarayananAZTP #process #verification
- Formal verification of analog circuits in the presence of noise and process variation (RN, BA, MHZ, ST, LCP), pp. 1309–1312.
- FM-2009-HasanAATA #random #reasoning
- Formal Reasoning about Expectation Properties for Continuous Random Variables (OH, NA, BA, ST, RA), pp. 435–450.
- IFM-2009-HasanAT #analysis #array #configuration management #fault #memory management #probability
- Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays (OH, NA, ST), pp. 277–291.
- CADE-2007-HasanT #formal method #probability
- Formalization of Continuous Probability Distributions (OH, ST), pp. 3–18.
- DATE-2007-Al-SammaneZT #design #verification
- A symbolic methodology for the verification of analog and mixed signal designs (GAS, MHZ, ST), pp. 249–254.
- IFM-2007-HasanT #cumulative #probability #using #verification
- Verification of Probabilistic Properties in HOL Using the Cumulative Distribution Function (OH, ST), pp. 333–352.
- DATE-2006-HabibiTSLM #performance #using #verification
- Efficient assertion based verification using TLM (AH, ST, AS, DL, OAM), pp. 106–111.
- DATE-2006-HassenT #on the #probability #term rewriting #verification
- On the numerical verification of probabilistic rewriting systems (JBH, ST), pp. 1223–1224.
- DATE-DF-2006-HabibiMT #finite #generative #state machine
- Generating finite state machines from SystemC (AH, HM, ST), pp. 76–81.
- DATE-2005-Abdel-HamidTA #design
- A Public-Key Watermarking Technique for IP Designs (ATAH, ST, EMA), pp. 330–335.
- DATE-2005-HabibiAMT04 #design #interface #on the #verification
- On the Design and Verification Methodology of the Look-Aside Interface (AH, AIA, OAM, ST), pp. 290–295.
- DATE-2005-HabibiT #design #modelling #transaction #verification
- Design for Verification of SystemC Transaction Level Models (AH, ST), pp. 560–565.
- SEFM-2003-GawanmehTW #design #using #verification
- Formal Verification of ASM Designs Using the MDG Tool (AG, ST, KW), pp. 210–219.
- IFM-2002-AkbarpourDT #fixpoint #formal method
- Formalization of Cadence SPW Fixed-Point Arithmetic in HOL (BA, AD, ST), pp. 185–204.
- IFM-2002-XiongCTB
- Formally Linking MDG and HOL Based on a Verified MDG System (HX, PC, ST, AB), pp. 205–224.
- CAV-1996-AnonBCCLSTXZ #design #tool support #verification
- MDG Tools for the Verification of RTL Designs (KDA, NB, EC, FC, ML, XS, ST, YX, ZZ), pp. 433–436.