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Travelled to:
4 × USA
Collaborated with:
Y.Ju D.Sengupta K.Kubiak S.Parkes W.K.Fuchs G.Hung Y.Wen K.Gallivan
Talks about:
increment (2) circuit (2) simul (2) relax (2) use (2) floorplan (1) waveform (1) techniqu (1) sensitiz (1) parallel (1)

Person: Resve A. Saleh

DBLP DBLP: Saleh:Resve_A=

Contributed to:

DAC 20082008
DAC 19921992
DAC 19911991
DAC 19901990

Wrote 5 papers:

DAC-2008-SenguptaS #design
Application-driven floorplan-aware voltage island design (DS, RAS), pp. 155–160.
DAC-1992-JuS #incremental #simulation #using
Incremental Circuit Simulation Using Waveform Relaxation (YCJ, RAS), pp. 8–11.
DAC-1992-KubiakPFS #evaluation
Exact Evaluation of Diagnostic Test Resolution (KK, SP, WKF, RAS), pp. 347–352.
DAC-1991-JuS #identification #incremental
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths (YCJ, RAS), pp. 541–546.
DAC-1990-HungWGS #parallel #simulation #using
Parallel Circuit Simulation Using Hierarchical Relaxation (GGH, YCW, KG, RAS), pp. 394–399.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.