BibSLEIGH — Proceedings of the 27th Design Automation Conference

Richard C. Smith
Proceedings of the 27th Design Automation Conference
DAC, 1990.

SYS

@proceedings{DAC-1990,
	acmid         = "123186",
	address       = "Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA",
	editor        = "Richard C. Smith",
	isbn          = "0-89791-363-9",
	publisher     = "{IEEE Computer Society Press}",
	title         = "{Proceedings of the 27th Design Automation Conference}",
	year          = 1990,
}

Contents (125 items)

DAC-1990-ArmstrongCSK #validation: The VHDL Validation Suite (JA, CC, SS, CK), pp. 2–7.
DAC-1990-IshiuraYY #behaviour #design #hardware #named #semantics: NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I (NI, HY, SY), pp. 8–13.
DAC-1990-DuttHG #behaviour #representation #synthesis: An Intermediate Representation for Behavioral Synthesis (NDD, TH, DG), pp. 14–19.
DAC-1990-KlingB #evolution #optimisation #standard: Optimization by Simulated Evolution with Applications to Standard Cell Placement (RMK, PB), pp. 20–25.
DAC-1990-SaabR #effectiveness #evolution #heuristic #layout #performance #probability #problem: Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems (YS, VBR), pp. 26–31.
DAC-1990-UptonSS #design #metaprogramming #standard: Integrated Placement for Mixed Macro Cell and Standard Cell Designs (MU, KS, SS), pp. 32–35.
DAC-1990-ChatterjeeH #approach #clustering: A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing (AC, RIH), pp. 36–39.
DAC-1990-BraceRB #implementation #performance: Efficient Implementation of a BDD Package (KSB, RLR, REB), pp. 40–45.
DAC-1990-BurchCMD #model checking #using #verification: Sequential Circuit Verification Using Symbolic Model Checking (JRB, EMC, KLM, DLD), pp. 46–51.
DAC-1990-MinatoIY #diagrams #performance: Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation (SiM, NI, SY), pp. 52–57.
DAC-1990-KuM #constraints #scheduling: Relative Scheduling Under Timing Constraints (DCK, GDM), pp. 59–64.
DAC-1990-HwangHL #constraints #heuristic #scheduling: Optimum and Heuristic Data Path Scheduling Under Resource Constraints (CTH, YCH, YLL), pp. 65–70.
DAC-1990-CloutierT #algorithm #scheduling: The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm (RJC, DET), pp. 71–76.
DAC-1990-PapachristouK #algorithm #linear #optimisation #scheduling: A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm (CAP, HK), pp. 77–83.
DAC-1990-DonathNABHKLM #using: Timing Driven Placement Using Complete Path Delays (WED, RJN, BKA, SEB, SYH, JMK, PL, RIM), pp. 84–89.
DAC-1990-SutanthavibulS #adaptation #layout: An Adaptive Timing-Driven Layout for High Speed VLSI (SS, ES), pp. 90–95.
DAC-1990-TeraiTS #algorithm #assurance #constraints #design #layout: A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint (MT, KT, KS), pp. 96–102.
DAC-1990-LinD: Performance-Driven Constructive Placement (IL, DHCD), pp. 103–106.
DAC-1990-BrasenB #algorithm #named #optimisation: MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing (DRB, MLB), pp. 107–110.
DAC-1990-SakallahMO #analysis #design: Analysis and Design of Latch-Controlled Synchronous Digital Circuits (KAS, TNM, KO), pp. 111–117.
DAC-1990-MartelloLC #using #verification: Timing Verification Using HDTV (ARM, SPL, DMC), pp. 118–123.
DAC-1990-McGeerB #analysis #network: Timing Analysis in Precharge/Unate Networks (PCM, RKB), pp. 124–129.
DAC-1990-IshiuraDY #diagrams #simulation #using: Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram (NI, YD, SY), pp. 130–135.
DAC-1990-CasottoNS #design: Design Management Based on Design Traces (AC, ARN, ALSV), pp. 136–141.
DAC-1990-WolfSBD #data transformation #framework: Meta Data Management in the NELSIS CAD Framework (PvdW, GWS, PB, PD), pp. 142–149.
DAC-1990-ChenG #behaviour #component #database #synthesis: An Intelligent Component Database for Behavioral Synthesis (GDC, DG), pp. 150–155.
DAC-1990-Liu #data transformation #design #framework: Design Data Management in a CAD Framework Environment (LCL), pp. 156–161.
DAC-1990-GrantD #algorithm #memory management #synthesis: Memory, Control and Communications Synthesis for Scheduled Algorithms (DMG, PBD), pp. 162–167.
DAC-1990-LyEG #synthesis: A Generalized Interconnect Model for Data Path Synthesis (TAL, WLE, EFG), pp. 168–173.
DAC-1990-McNallC #architecture #automation #pipes and filters #synthesis: Automatic Operator Configuration in the Synthesis of Pipelined Architectures (KNM, AEC), pp. 174–179.
DAC-1990-WangW #algorithm #optimisation: An Optimal Algorithm for Floorplan Area Optimization (TCW, DFW), pp. 180–186.
DAC-1990-SutanthavibulSR #approach #design #optimisation: An Analytical Approach to Floorplan Design and Optimization (SS, ES, JBR), pp. 187–192.
DAC-1990-Wang #layout: Pad Placement and Ring Routing for Custom Chip Layout (DCW), pp. 193–199.
DAC-1990-Spreitzer #design: Comparing Structurally Different Views of a VLSI Design (MS), pp. 200–212.
DAC-1990-GhoshDN #verification: Verification of Interacting Sequential Circuits (AG, SD, ARN), pp. 213–219.
DAC-1990-DevadasK #logic #optimisation #robust #synthesis: Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits (SD, KK), pp. 221–227.
DAC-1990-KeutzerMS: Is Redundancy Necessary to Reduce Delay (KK, SM, AS), pp. 228–234.
DAC-1990-AgrawalC #specification #synthesis: Test Function Specification in Synthesis (VDA, KTC), pp. 235–240.
DAC-1990-Domic #layout #synthesis: Layout Synthesis of MOS Digital Cells (AD), pp. 241–245.
DAC-1990-SuzukiO #design #online: A Practical Online Design Rule Checking System (GS, YO), pp. 246–252.
DAC-1990-CarlsonR #algorithm #design #evaluation #parallel #performance #verification: Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW (ECC, RAR), pp. 253–259.
DAC-1990-Tonkin #message passing #multi: Circuit Extraction on a Message-Based Multiprocessor (BAT), pp. 260–265.
DAC-1990-Barnes #named: SKILL: A CAD System Extension Language (TJB), pp. 266–271.
DAC-1990-Jabri #knowledge-based #named #prolog: BREL — a Prolog Knowledge-based System Shell for VLSI CAD (MAJ), pp. 272–277.
DAC-1990-FidukKKP #design #framework #perspective: Design Methodology Management — a CAD Framework Initiative Perspective (KWF, SK, MK, EBP), pp. 278–283.
DAC-1990-SatoYMF #diagrams: Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams (HS, YY, YM, MF), pp. 284–289.
DAC-1990-MalikBNS #logic #multi: Reduced Offsets for Two-Level Multi-Valued Logic Minimization (AAM, RKB, ARN, ALSV), pp. 290–296.
DAC-1990-SavojB #multi #network #using: The Use of Observability and External Don’t Cares for the Simplification of Multi-Level Networks (HS, RKB), pp. 297–301.
DAC-1990-ChengA #complexity #multi: An Entropy Measure for the Complexity of Multi-Output Boolean Functions (KTC, VDA), pp. 302–305.
DAC-1990-CaiNSM #assembly #layout #performance: A Data Path Layout Assembler for High Performance DSP Circuits (HC, SN, PS, HDM), pp. 306–311.
DAC-1990-HillS #synthesis: Global Routing Considerations in a Cell Synthesis System (DDH, DS), pp. 312–316.
DAC-1990-HillP #benchmark #metric #synthesis: Benchmarks for Cell Synthesis (DDH, BP), pp. 317–320.
DAC-1990-OkuboWW #algorithm: New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion (TO, TW, KW), pp. 321–326.
DAC-1990-WeyDC #design: Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement (CLW, JD, TYC), pp. 327–332.
DAC-1990-ForsytheAYAG #development #simulation: NASFLOW, a Simulation Tool for Silicon Technology Development (DDF, APA, CSY, SA, BG), pp. 333–337.
DAC-1990-ChenM #multi #network #optimisation: Timing Optimization for Multi-Level Combinational Networks (KCC, SM), pp. 339–344.
DAC-1990-KageyamaMS #algorithm #approach #linear #logic #optimisation #programming: Logic Optimization Algorithm by Linear Programming Approach (NK, CM, TS), pp. 345–348.
DAC-1990-LinMK #design #optimisation #standard: Delay and Area Optimization in Standard-Cell Design (SL, MMS, ESK), pp. 349–352.
DAC-1990-Chan #algorithm #logic: Algorithms for Library-Specific Sizing of Combinational Logic (PKC), pp. 353–356.
DAC-1990-SinghS #algorithm #heuristic #problem: A Heuristic Algorithm for the Fanout Problem (KJS, ALSV), pp. 357–360.
DAC-1990-Fishburn #heuristic #how #logic: A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between (JPF), pp. 361–364.
DAC-1990-AbouzeidSSP #multi #synthesis: Multilevel Synthesis Minimizing the Routing Factor (PA, KS, GS, FP), pp. 365–368.
DAC-1990-Onozawa #constraints #layout: Layout Compaction with Attractive and Repulsive Constraints (AO), pp. 369–374.
DAC-1990-Marple: A Hierarchy Preserving Hierarchical Compactor (DM), pp. 375–381.
DAC-1990-LoV #algorithm: An O(n1.5logn) 1-d Compaction Algorithm (CYL, RV), pp. 382–387.
DAC-1990-MatsumotoWUSHM #generative #layout: Datapath Generator Based on Gate-Level Symbolic Layout (NM, YW, KU, YS, HH, SM), pp. 388–393.
DAC-1990-HungWGS #parallel #simulation #using: Parallel Circuit Simulation Using Hierarchical Relaxation (GGH, YCW, KG, RAS), pp. 394–399.
DAC-1990-Yang #named #parallel: PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors (GCY), pp. 400–405.
DAC-1990-McCormickA #analysis: Waveform Moment Methods for Improved Interconnection Analysis (SPM, JA), pp. 406–412.
DAC-1990-AdamiakAPRW #simulation: System Simulation of Printed Circuit Boards Including Packages and Connectors (KA, RA, JP, CR, AW), pp. 413–418.
DAC-1990-BowerSW #framework #generative #industrial #layout: A Framework for Industrial Layout Generators (WB, CS, WW), pp. 419–424.
DAC-1990-Soukup #algorithm #database: Organized C: A Unified Method of Handling Data in CAD Algorithms and Databases (JS), pp. 425–430.
DAC-1990-ChungK #design #object-oriented: An Object-Oriented VHDL Design Environment (MJC, SK), pp. 431–436.
DAC-1990-FeghhiMK #design #kernel #object-oriented #process: An Object-Oriented Kernel for an Integrated Design and Process Planning System (SJF, MMM, RLK), pp. 437–443.
DAC-1990-PotasmanLNG #synthesis: Percolation Based Synthesis (RP, JL, AN, DG), pp. 444–449.
DAC-1990-CompasanoB #algorithm #scheduling #synthesis #using: Synthesis Using Path-Based scheduling: algorithms and Exercises (RC, RAB), pp. 450–455.
DAC-1990-ScheichenzuberGLM #behaviour #data flow #hardware #synthesis: Global Hardware Synthesis from Behavioral Dataflow Descriptions (JS, WG, UL, SM), pp. 456–461.
DAC-1990-SinghC #layout #matrix #order: A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.
DAC-1990-JustASS #generative #logic #named: PALACE: A Kayout Generator for SCVS Logic Blocks (KMJ, EA, WLS, AS), pp. 468–473.
DAC-1990-HsiehHLH #generative #layout #named: LiB: A Cell Layout Generator (YCH, CYH, YLL, YCH), pp. 474–479.
DAC-1990-MaurerW #simulation: Techniques for Unit-Delay Compiled Simulation (PMM, ZW), pp. 480–484.
DAC-1990-SubramanianZ #distributed #logic #parallel #simulation: Distributed and Parallel Demand Driven Logic Simulation (KS, MRZ), pp. 485–490.
DAC-1990-WangM #logic #named #simulation: LECSIM: A Levelized Event Driven Compiled Logic Simulation (ZW, PMM), pp. 491–496.
DAC-1990-HuangCLH: Data Path Allocation Based on Bipartite Weighted Matching (CYH, YSC, YLL, YCH), pp. 499–504.
DAC-1990-Woo #synthesis: A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System (NSW), pp. 505–510.
DAC-1990-KucukcakarP #trade-off #using: Data Path Tradeoffs Using MABAL (KK, ACP), pp. 511–516.
DAC-1990-Bryant #simulation: Symbolic Simulation — Techniques and Applications (REB), pp. 517–521.
DAC-1990-ParkM #generative #logic #performance #testing: An Efficient Delay Test Generation System for Combinational Logic Circuits (ESP, MRM), pp. 522–528.
DAC-1990-Ito #automation #testing: Automatic Incorporation of On-Chip Testability Circuits (NI), pp. 529–534.
DAC-1990-NiermannCP #fault #memory management #named #performance #proving: Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator (TMN, WTC, JHP), pp. 535–540.
DAC-1990-BreternitzS #architecture #synthesis: Architecture Synthesis of High-Performance Application-Specific Processors (MBJ, JPS), pp. 542–548.
DAC-1990-SarmaDNH #industrial #synthesis: High-Level Synthesis: Technology Transfer to Industry (RCS, MDD, NCN, GH), pp. 549–554.
DAC-1990-EdmondGSB #automation #dependence #design #named: ASSURE: Automated Design for Dependability (PE, APG, DPS, AAB), pp. 555–560.
DAC-1990-ChoudhuryS #constraints #generative: Constraint Generation for Routing Analog Circuits (UC, ALSV), pp. 561–566.
DAC-1990-GreeneRKG: Segmented Channel Routing (JWG, VPR, SK, AEG), pp. 567–572.
DAC-1990-JacksonSK: Clock Routing for High-Performance ICs (MABJ, AS, ESK), pp. 573–579.
DAC-1990-GhoshDN90a #generative #logic #testing: Sequential Test Generation at the Register-Transfer and Logic Levels (AG, SD, ARN), pp. 580–586.
DAC-1990-WardA #behaviour #fault #simulation: Behavioral Fault Simulation in VHDL (PCW, JRA), pp. 587–593.
DAC-1990-KundaARN #generative #testing #using: Speed Up of Test Generation Using High-Level Primitives (RPK, JAA, BDR, PN), pp. 594–599.
DAC-1990-AsharDN #approach #composition: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines (PA, SD, ARN), pp. 601–606.
DAC-1990-DeyBK #clustering: Corolla Based Circuit Partitioning and Resynthesis (SD, FB, GK), pp. 607–612.
DAC-1990-FrancisRC #array #named #programmable: Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays (RJF, JR, KC), pp. 613–619.
DAC-1990-MurgaiNSBS #array #logic #programmable #synthesis: Logic Synthesis for Programmable Gate Arrays (RM, YN, NVS, RKB, ALSV), pp. 620–625.
DAC-1990-SchieleKJK #design #industrial: A Gridless Router for Industrial Design Rules (WLS, TK, KMJ, FHK), pp. 626–631.
DAC-1990-Hojati #layout #optimisation: Layout Optimization by Pattern Modification (RH), pp. 632–637.
DAC-1990-CaiW #algorithm #layout: A Channel/Switchbox Definition Algorithm for Building-Block Layout (YC, DFW), pp. 638–641.
DAC-1990-EdahiroY #algorithm #standard: New Placement and Global Routing Algorithms for Standard Cell Layouts (ME, TY), pp. 642–645.
DAC-1990-SatoKO #hardware #implementation #memory management: A Hardware Implementation of Gridless Routing Based on Content Addressable Memory (MS, KK, TO), pp. 646–649.
DAC-1990-BrouwerB #named #parallel: PHIGURE: A Parallel Hierarchical Global Router (RJB, PB), pp. 650–653.
DAC-1990-ChakradharAB #automation #generative #polynomial #programming #testing #using: Automatic Test Generation Using Quadratic 0-1 Programming (STC, VDA, MLB), pp. 654–659.
DAC-1990-LeeH #automation #fault #generative #named #performance: SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits (HKL, DSH), pp. 660–666.
DAC-1990-GiraldiB #automation #future of #generative #named: EST: The New Frontier in Automatic Test-Pattern Generation (JG, MLB), pp. 667–672.
DAC-1990-ButlerM #design #fault #performance: The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design (KMB, MRM), pp. 673–678.
DAC-1990-WhitcombN #data type #synthesis: Abstract Data Types and High-Level Synthesis (GSW, ARN), pp. 680–685.
DAC-1990-DagaB: Failure Recovery in the MICON System (AJD, WPB), pp. 686–691.
DAC-1990-Wolf #automaton #behaviour #network #synthesis: The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines (WW), pp. 692–697.
DAC-1990-GidwaniS #named: MISER: An Integrated Three Layer Gridless Channel Router and Compactor (RAG, NAS), pp. 698–703.
DAC-1990-KatsadasK #multi: A Multi-Layer Router Utilizing Over-Cell Areas (EK, EK), pp. 704–708.
DAC-1990-CongPL #algorithm #design #modelling #standard: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design (JC, BP, CLL), pp. 709–715.
DAC-1990-HwangLSW #fault #parallel: A Parallel Pattern Mixed-Level Fault Simulator (TSH, CLL, WZS, CPW), pp. 716–719.
DAC-1990-RamakrishnanK #algorithm: Extension of the Critical Path Tracing Algorithm (TR, LK), pp. 720–723.
DAC-1990-UpadhyayaT #case study: BIST PLAs, Pass or Fail — A Case Study (SJU, JAT), pp. 724–727.
DAC-1990-MaoC #fault #testing: A Variable Observation Time Method for Testing Delay Faults (WM, MDC), pp. 728–731.
DAC-1990-KuoLW #analysis #fault: A Fault Analysis Method for Synchronous Sequential Circuits (TYK, JYL, JFW), pp. 732–735.
DAC-1990-Chakravarty #identification #on the: On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (SC), pp. 736–739.

Richard C. SmithProceedings of the 27th Design Automation ConferenceDAC, 1990.

Contents (125 items)

Richard C. Smith
Proceedings of the 27th Design Automation Conference
DAC, 1990.