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Travelled to:
1 × USA
Collaborated with:
T.H.Edmondson
Talks about:
hierarch (1) system (1) layout (1) verif (1) vlsi (1) cost (1) low (1)

Person: Richard M. Jennings

DBLP DBLP: Jennings:Richard_M=

Contributed to:

DAC 19811981

Wrote 1 papers:

DAC-1981-EdmondsonJ #layout #low cost #verification
A low cost hierarchical system for VLSI layout and verification (THE, RMJ), pp. 505–510.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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