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Travelled to:
1 × USA
Collaborated with:
R.S.Gyurcsik
Talks about:
test (2) circuit (1) integr (1) analog (1) order (1) optim (1) minim (1) time (1)

Person: Scott D. Huss

DBLP DBLP: Huss:Scott_D=

Contributed to:

DAC 19911991

Wrote 1 papers:

DAC-1991-HussG #testing
Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time (SDH, RSG), pp. 494–499.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.