Travelled to:2 × France
3 × Germany
Collaborated with:J.Segura B.Alorda J.L.Rosselló G.Torrens C.Carmona S.Barcelo X.Gili C.d.Benito M.Rosales V.Canals A.Keshavarzi
Talks about:stabil (3) power (3) sram (3) thermal (2) resist (2) improv (2) critic (2) optim (2) model (2) embed (2)
Person: Sebastiàn A. Bota
DBLP: Bota:Sebasti=agrave=n_A=
Contributed to:
20142011201020072005Wrote 7 papers:
- DATE-2014-AlordaCB #embedded #power management #reliability
- Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications (BA, CC, SAB), pp. 1–6.
- DATE-2011-AlordaTBS #embedded #optimisation #using
- Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation (BA, GT, SAB, JS), pp. 986–991.
- DATE-2011-BarceloGBS #estimation #performance #scalability
- An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation (SB, XG, SAB, JS), pp. 1602–1607.
- DATE-2010-AlordaTBS #power management
- Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs (BA, GT, SAB, JS), pp. 429–434.
- DATE-2007-RosselloBBS #statistics #testing
- Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs (JLR, CdB, SAB, JS), pp. 1271–1276.
- DATE-2005-BotaRRS #testing
- Smart Temperature Sensor for Thermal Testing of Cell-Based ICs (SAB, MR, JLR, JS), pp. 464–465.
- DATE-2005-RosselloCBKS #concurrent #performance
- A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs (JLR, VC, SAB, AK, JS), pp. 206–211.