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Travelled to:
1 × Italy
2 × Germany
5 × USA
Collaborated with:
O.Tkachuk A.J.Hu M.Fujita G.Li I.Ghosh D.W.Currie V.Boppana K.Takayama P.Li G.Sawaya G.Gopalakrishnan
Talks about:
generat (5) softwar (3) verif (3) environ (2) automat (2) formal (2) applic (2) model (2) check (2) autom (2)

Person: Sreeranga P. Rajan

DBLP DBLP: Rajan:Sreeranga_P=

Contributed to:

PPoPP 20122012
CAV 20112011
FASE 20112011
ASE 20072007
ISSTA 20062006
DAC 20002000
CAV 19991999
FM-Trends 19981998

Wrote 8 papers:

PPoPP-2012-LiLSGGR #generative #named #testing #verification
GKLEE: concolic verification and test generation for GPUs (GL, PL, GS, GG, IG, SPR), pp. 215–224.
CAV-2011-LiGR #automation #c++ #execution #generative #named #source code #symbolic computation #testing
KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs (GL, IG, SPR), pp. 609–615.
FASE-2011-TkachukR #analysis #automation #generative #web
Automated Driver Generation for Analysis of Web Applications (OT, SPR), pp. 326–340.
ASE-2007-TkachukR #composition #generative #model checking #slicing
Combining environment generation and slicing for modular software model checking (OT, SPR), pp. 401–404.
ISSTA-2006-TkachukR #automation #generative
Application of automated environment generation to commercial software (OT, SPR), pp. 203–214.
DAC-2000-CurrieHR #automation #verification
Automatic formal verification of DSP software (DWC, AJH, SPR), pp. 130–135.
CAV-1999-BoppanaRTF #model checking
Model Checking Based on Sequential ATPG (VB, SPR, KT, MF), pp. 418–430.
FM-1998-FujitaRH #case study #experience #parallel #protocol #verification
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (MF, SPR, AJH), pp. 281–295.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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