Travelled to:1 × Italy
2 × Germany
5 × USA
Collaborated with:O.Tkachuk A.J.Hu M.Fujita G.Li I.Ghosh D.W.Currie V.Boppana K.Takayama P.Li G.Sawaya G.Gopalakrishnan
Talks about:generat (5) softwar (3) verif (3) environ (2) automat (2) formal (2) applic (2) model (2) check (2) autom (2)
Person: Sreeranga P. Rajan
DBLP: Rajan:Sreeranga_P=
Contributed to:
2012
2011
2011
2007
2006
20001999
1998Wrote 8 papers:
- PPoPP-2012-LiLSGGR #generative #named #testing #verification
- GKLEE: concolic verification and test generation for GPUs (GL, PL, GS, GG, IG, SPR), pp. 215–224.
- CAV-2011-LiGR #automation #c++ #execution #generative #named #source code #symbolic computation #testing
- KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs (GL, IG, SPR), pp. 609–615.
- FASE-2011-TkachukR #analysis #automation #generative #web
- Automated Driver Generation for Analysis of Web Applications (OT, SPR), pp. 326–340.
- ASE-2007-TkachukR #composition #generative #model checking #slicing
- Combining environment generation and slicing for modular software model checking (OT, SPR), pp. 401–404.
- ISSTA-2006-TkachukR #automation #generative
- Application of automated environment generation to commercial software (OT, SPR), pp. 203–214.
- DAC-2000-CurrieHR #automation #verification
- Automatic formal verification of DSP software (DWC, AJH, SPR), pp. 130–135.
- CAV-1999-BoppanaRTF #model checking
- Model Checking Based on Sequential ATPG (VB, SPR, KT, MF), pp. 418–430.
- FM-1998-FujitaRH #case study #experience #parallel #protocol #verification
- Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol (MF, SPR, AJH), pp. 281–295.