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Travelled to:
1 × Germany
1 × USA
Collaborated with:
E.T.A.F.Jacobs J.A.G.Jess K.Kalafala R.H.J.M.Otten C.Visweswariah
Talks about:
circuit (2) parametr (1) statist (1) predict (1) static (1) leakag (1) integr (1) yield (1) stand (1) power (1)

Person: Srinath R. Naidu

DBLP DBLP: Naidu:Srinath_R=

Contributed to:

DAC 20032003
DATE 20012001

Wrote 2 papers:

DAC-2003-JessKNOV #parametricity #predict #statistics
Statistical timing for parametric yield prediction of digital integrated circuits (JAGJ, KK, SRN, RHJMO, CV), pp. 932–937.
DATE-2001-NaiduJ #power management
Minimizing stand-by leakage power in static CMOS circuits (SRN, ETAFJ), pp. 370–376.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.