Travelled to:3 × France
Collaborated with:∅ W.J.Bainbridge L.A.Plana S.Tan W.Yen M.Merrett P.Asenov Y.Wang M.Zwolinski D.Reid C.Millar S.Roy Z.Liu A.Asenov
Talks about:design (2) time (2) chip (2) architectur (1) smartcard (1) processor (1) asynchron (1) parallel (1) variabl (1) synthes (1)
Person: Stephen B. Furber
DBLP: Furber:Stephen_B=
Contributed to:
201120041998Wrote 4 papers:
- DATE-2011-Furber #architecture
- Biologically-inspired massively-parallel architectures — Computing beyond a million processors (SBF), p. 1.
- DATE-2011-MerrettAWZRMRLFA #analysis #modelling #monte carlo #performance #statistics #variability
- Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis (MM, PA, YW, MZ, DR, CM, SR, ZL, SBF, AA), pp. 1537–1540.
- DATE-DF-2004-BainbridgePF #design #self #using
- The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip (WJB, LAP, SBF), pp. 274–279.
- DATE-1998-TanFY #design
- The Design of an Asynchronous VHDL Synthesizer (SYT, SBF, WFY), pp. 44–51.