BibSLEIGH — Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Designers’ Forum

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Designers’ Forum
DATE DF, 2004.

SYS

@proceedings{DATE-DF-2004,
	address       = "Paris, France",
	isbn          = "0-7695-2085-5",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Designers’ Forum}",
	year          = 2004,
}

Contents (61 items)

DATE-DF-2004-AitkenM #dependence #design: From Working Design Flow to Working Chips: Dependencies and Impacts of Methodology Decisions (RCA, FM), p. 2.
DATE-DF-2004-LoukusaPRRV #design #perspective: Systems on Chips Design: System Manufacturer Point of View (VL, HP, AR, TR, OV), pp. 3–4.
DATE-DF-2004-Dandia #design #performance: Package Design for High Performance ICs (SD), p. 5.
DATE-DF-2004-Eklow #question #testing: IP Testing — The Future Differentiator? (BE), pp. 6–9.
DATE-DF-2004-JuniorC #design #low cost #statistics: Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs (AAdSJ, LC), pp. 10–15.
DATE-DF-2004-Tissafi-DrissiOG #automation #design #framework #multi #named #performance #platform: RUNE: Platform for Automated Design of Integrated Multi-Domain Systems. Application to High-Speed CMOS Photoreceiver Front-Ends (FTD, IO, FG), pp. 16–21.
DATE-DF-2004-ChenYSMGH #design #using: Demonstration of a SiGe RF LNA Design Using IBM Design Kits in 0.18um SiGe BiCMOS Technology (YC, XY, DS, JM, JG, DLH), pp. 22–27.
DATE-DF-2004-Saul #power management: Low Power Analogue 90 Degree Phase Shifter (PHS), pp. 28–33.
DATE-DF-2004-Horsky #precise: A 16 Bit + Sign Monotonic Precise Current DAC for Sensor Applications (PH), pp. 34–38.
DATE-DF-2004-BantasKL #design #modelling: An Inductance Modeling Flow Seamlessly Integrated in the RF IC Design Chain (SB, YK, AL), pp. 39–45.
DATE-DF-2004-WortmannSM #architecture #performance: A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core (AW, SS, MM), pp. 46–51.
DATE-DF-2004-PanatoSWJRB #design #multi #pipes and filters: Design of Very Deep Pipelined Multipliers for FPGAs (AP, SVS, FRW, MOJ, RR, SB), pp. 52–57.
DATE-DF-2004-PaulinPBLL #framework #multi #performance #platform: Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding (PGP, CP, EB, ML, DL), pp. 58–63.
DATE-DF-2004-NiranjanW #design: Islands of Synchronicity, a Design Methodology for SoC Design (APN, PCW), pp. 64–69.
DATE-DF-2004-DaddaMO #design: The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512) (LD, MM, JO), pp. 70–75.
DATE-DF-2004-LinXW #embedded: LZW-Based Code Compression for VLIW Embedded Systems (CHL, YX, WW), pp. 76–81.
DATE-DF-2004-MoignePC #realtime #simulation: A Generic RTOS Model for Real-time Systems Simulation with SystemC (RLM, OP, JPC), pp. 82–87.
DATE-DF-2004-CoccoDHHH #architecture #scalability: A Scalable Architecture for LDPC Decodin (MC, JD, MJMH, AH, JH), pp. 88–95.
DATE-DF-2004-SchmittR #design #low cost #prototype #using #verification: Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments (SS, WR), pp. 96–101.
DATE-DF-2004-KruppMO #model checking #refinement: Formal Refinement and Model Checking of an Echo Cancellation Unit (AK, WM, IO), pp. 102–107.
DATE-DF-2004-GoelCMNO #design #framework #platform: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip (SKG, KC, EJM, TN, SO), pp. 108–113.
DATE-DF-2004-Thiel #validation: Have I Really Met Timing? — Validating PrimeTime Timing Reports with Spice (TT), pp. 114–119.
DATE-DF-2004-VorisekKF #testing: At-Speed Testing of SOC ICs (VV, TK, HF), pp. 120–125.
DATE-DF-2004-ChenLHBB #design #network: Utilizing Formal Assertions for System Design of Network Processors (XC, YL, HH, LNB, FB), pp. 126–133.
DATE-DF-2004-DiazS #physics: Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit (JCD, MS), pp. 134–139.
DATE-DF-2004-Auletta: Expert System Perimeter Block Placement Floorplanning (RA), pp. 140–143.
DATE-DF-2004-ElfadelDKRS: A CAD Methodology and Tool for the Characterization of Wide On-Chip Buses (IME, AD, GVK, BR, HS), pp. 144–149.
DATE-DF-2004-Ruiz-AmayaRMFRPR #matlab #synthesis: MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators (JRA, JLdlR, FM, FVF, RdR, MBPV, ÁRV), pp. 150–155.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-DF-2004-VarmaB #compilation #embedded #java: Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems (AV, SSB), pp. 161–167.
DATE-DF-2004-FummiMPPRT #embedded: Heterogeneous Co-Simulation of Networked Embedded Systems (FF, SM, GP, MP, FR, MT), pp. 168–173.
DATE-DF-2004-CoppolaCGMP #framework #modelling #named #simulation: OCCN: A Network-On-Chip Modeling and Simulation Framework (MC, SC, MDG, GM, FP), pp. 174–179.
DATE-DF-2004-BruschiB #communication #design #synthesis: A Design Methodology for the Exploitation of High Level Communication Synthesis (FB, MB), pp. 180–185.
DATE-DF-2004-PapaefstathiouKZ #network #performance: Software Processing Performance in Network Processors (IP, GK, NZ), pp. 186–191.
DATE-DF-2004-BerensKW #architecture #mobile: Channel Decoder Architecture for 3G Mobile Wireless Terminals (FB, GK, NW), pp. 192–197.
DATE-DF-2004-ZeferinoKS #named: RASoC: A Router Soft-Core for Networks-on-Chip (CAZ, MEK, AAS), pp. 198–205.
DATE-DF-2004-CilardoMRS #composition #configuration management #hardware: Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware (AC, AM, LR, GPS), pp. 206–211.
DATE-DF-2004-FaroukS #architecture #design #implementation: Design and Implementation of a Secret Key Steganographic Micro-Architecture Employing FPGA (HAF, MS), pp. 212–217.
DATE-DF-2004-FerrerGFAC #implementation #logic #named #network #programmable: NeuroFPGA — Implementing Artificial Neural Networks on Programmable Logic Devices (DF, RG, RF, JPA, RC), pp. 218–223.
DATE-DF-2004-PortoA #2d #architecture #implementation: Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation (RECP, LVA), pp. 224–229.
DATE-DF-2004-QuaxHM #configuration management #implementation #scalability: A Scalable Implementation of a Reconfigurable WCDMA Rake Receiver (MQ, JH, JLvM), pp. 230–235.
DATE-DF-2004-ChuDPSL #architecture #tool support: Customisable EPIC Processor: Architecture and Tools (WWSC, RGD, SP, SPS, WL), pp. 236–241.
DATE-DF-2004-BoschettiSB #architecture #configuration management #image #runtime: A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications (MRB, ISS, SB), pp. 242–247.
DATE-DF-2004-LettninBBGR #case study #design #embedded #network #synthesis: Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks (DL, AGB, MB, JG, WR), pp. 248–255.
DATE-DF-2004-BlancGG #architecture #case study #experience #validation: Experiences during the Experimental Validation of the Time-Triggered Architecture (SB, JG, PJG), pp. 256–261.
DATE-DF-2004-SchubertHGAN #design #evaluation: Evaluation of a Refinement-Driven SystemC™-Based Design Flow (TS, JH, JG, JEA, WN), pp. 262–267.
DATE-DF-2004-BannowH #design #evaluation #hardware #object-oriented: Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications (NB, KH), pp. 268–273.
DATE-DF-2004-BainbridgePF #design #self #using: The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip (WJB, LAP, SBF), pp. 274–279.
DATE-DF-2004-RenWBLLD #design: A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications (BR, AW, JB, KL, WL, WWMD), pp. 280–285.
DATE-DF-2004-AbrahamR #design #integration: Qualification and Integration of Complex I/O in SoC Design Flows (JA, GR), pp. 286–293.
DATE-DF-2004-HollevoetDDCL #memory management: A Power Optimized Display Memory Organization for Handheld User Terminal (LH, AD, KD, FC, FL), pp. 294–299.
DATE-DF-2004-NeffeRSWRM #energy #estimation #modelling #power management #smarttech: Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (UN, KR, CS, RW, ER, AM), pp. 300–305.
DATE-DF-2004-BrandoleseFSS #analysis #energy #modelling #program transformation #source code: Analysis and Modeling of Energy Reducing Source Code Transformations (CB, WF, FS, DS), pp. 306–311.
DATE-DF-2004-MenichelliOBDB #architecture #design #multi #power management: A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design (FM, MO, LB, MD, LB), pp. 312–317.
DATE-DF-2004-BonaZZ #industrial #modelling #simulation: System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip (AB, VZ, RZ), pp. 318–323.
DATE-DF-2004-FlautnerFRP #energy #named #performance #scalability: IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling (KF, DF, DR, DIP), pp. 324–329.
DATE-DF-2004-Werner #quality #question: Can IP Quality be Objectively Measured? (KW), pp. 330–331.
DATE-DF-2004-BaileyMBLA #design #verification: Improving Design and Verification Productivity with VHDL-200x (SB, EM, JB, JL, PJA), pp. 332–335.
DATE-DF-2004-DaglioIRRS #component #performance #simulation: Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
DATE-DF-2004-HeckerCLBLO #development #library: VHDL-AMS Library Development for Pacemaker Applications (BH, MC, ML, EB, LL, JO), pp. 338–341.
DATE-DF-2004-FummiMMPP #analysis #architecture #industrial #modelling #network: Modeling and Analysis of Heterogeneous Industrial Networks Architectures (FF, SM, MM, GP, MP), pp. 342–344.

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Designers’ ForumDATE DF, 2004.

Contents (61 items)

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Designers’ Forum
DATE DF, 2004.